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19-100133; rev 1, 9/17 general description the MAX30001 is a complete, biopotential and bioimpedance (bioz), analog front-end (afe) solution for wearable applications. it offers high performance for clinical and fitness applications, with ultra-low power for long battery life. the MAX30001 is a single biopotential channel providing electrocardiogram (ecg) waveforms, heart rate and pacemaker edge detection, and a single bioimpedance channel capable of measuring respiration. the biopotential and bioimpedance channels have esd protection, emi filtering, internal lead biasing, dc leads- off detection, ultra-low-power, leads-on detection during standby mode, and extensive calibration voltages for built-in self-test. soft power-up sequencing ensures no large transients are injected into the electrodes. both channels also have high input impedance, low noise, high cmrr, programmable gain, various low-pass and high-pass filter options, and a high resolution analog-to- digital converter. the biopotential channel is dc coupled, can handle large electrode voltage offsets, and has a fast recovery mode to quickly recover from overdrive conditions, such as defibrillation and electro-surgery. the bioimpedance channel includes integrated programmable current drive, works with common electrodes, and has the flexibility for 2 or 4 electrode measurements. it also has ac lead off detection. the MAX30001 is available in a 28-pin tqfn and 30-bump wafer-level package (wlp), operating over the 0c to +70c commercial temperature range. applications single-lead event monitors for arrhythmia detection single-lead wireless patches for in-patient/out-patient monitoring chest band heart rate monitors for fitness applications bio authentication and ecg-on-demand applications respiration and hydration monitors impedance based heart rate detection benefts and features clinical-grade ecg and bioz afe with high resolution data converter ? 15.9 bits enob with 3.1v pp (typ) noise for ecg ? 17 bits enob with 1.1v pp noise for bioz better dry starts due to much improved real world cmrr and high input impedance ? fully differential input structure with cmrr > 100db offers better common-mode to differential mode conversion due to high input impedance high input impedance > 1g for extremely low common-to-differential mode minimum signal attenuation at the input during dry start due to high electrode impedance high dc offset range of 650mv (1.8v, typ) allows to be used with wide variety of electrodes high ac dynamic range of 65mv pp for ecg and 100mv pp for bioz will help prevent saturation in the presence of motion/direct electrode hits longer battery life compared to competing solutions ? 85w at 1.1v supply voltage for ecg ? 158w at 1.1v supply voltage for bioz leads-on interrupt feature allows to keep c in deep sleep mode until valid lead condition is detected ? lead-on detect current: 0.7a (typ) built-in heart rate detection with interrupt feature eliminates the need to run hr algorithm on the controller ? robust r-r detection in high motion environment at extremely low power configurable interrupts allows the c wake-up only on every heart beat reducing the overall system power high accuracy allows for more physiological data extractions 32-word ecg and 8-word bioz fifos allows the mcu to stay powered down for 256ms with full data acquisition high-speed spi interface shutdown current of 0.5a (typ) ordering information appears at end of data sheet. MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe
clock divider w/ phase adjust esd, emi, input mux, dc lead check decimation filter 20-bit adc input amp aaf bip bin drvp drvn pga bioimpedance channel MAX30001 avdd bandgap common-mode buffer biasing pll support circuitry f hfc f clk reference buffer spi interface, ecg fifo, and registers dvdd sequencer ovdd dgnd agnd csb sdi sclk sdo intb int2b fclk vcm vbg vref cpll 20-bit push/pull current source f -3db =600hz -40db/dec selectable phase rbias fast settling r-to-r detector esd, emi, input mux, dc lead check decimation filter 18-bit adc input amp ecgp ecgn capp capn pga biopotential channel 18-bit 14-bit aaf f -3db =600hz -40db/dec pga respiration cancel, derivative, sample/hold window compare & resync buffer aout mux pace detect channel pacep pacen lpf lpf input amp hpf -20db/dec pol. sw. functional diagram maxim integrated 2 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
avdd to agnd .................................................... -0.3v to +2.0v dvdd to dgnd .................................................... -0.3v to +2.0v avdd to dvdd .................................................... -0.3v to +0.3v ovdd to dgnd ................................................... -0.3v to +3.6v agnd to dgnd ................................................... -0.3v to +0.3v csb, sclk, sdi, fclk to dgnd ....................... -0.3v to +3.6v sdo, intb, int2b to dgnd ........ -0.3v to the lower of (3.6v and ovdd + 0.3v) all other pins to agnd ......... -0.3v to the lower of (2.0v and avdd + 0.3v) maximum current into any pin ......................................... 50ma continuous power dissipation (t a = +70oc) 28-pin tqfn (derate 34.5mw/oc above +70oc) .......................... 2758.6mw 30-bump wlp (derate 24.3mw/oc above +70oc) .......................... 1945.5mw operating temperature range ............................... 0oc to +70c junction temperature ...................................................... +150c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10sec) ............................. +300c soldering temperature (reflow) ....................................... +260c tqfn junction-to-ambient thermal resistance ( ja ) .......... 29c/w junction-to-case thermal resistance ( jc ) ................. 2c/w wlp junction-to-ambient thermal resistance ( ja ) .......... 44c/w (note 1) (v dvdd = v avdd = +1.1v to +2.0v, v ovdd = +1.65v to +3.6v, f fclk = 32.768khz, ln_bioz = 1, t a = t min to t max , unless otherwise noted. typical values are at v dvdd = v avdd = +1.8v, v ovdd = +2.5v, t a = +25c.) (note 2) parameter symbol conditions min typ max units ecg channel ac di f ferential input range v a vdd = +1.1 v , thd < 0.3% -15 +15 mv pp v a vdd = +1.8 v , thd < 0.3% 32.5 dc differential input range v a vdd = +1.1 v , shift from nominal gain < 2% -300 +300 mv v a vdd = +1.8v 650 common mode input range v a vdd = +1.1 v , from v mid , shift from nominal gain < 2% -150 +150 mv v a vdd = +1.8 v , from v mid , shift from nominal gain < 2% 550 common mode rejection ratio cmrr 0 source impedance, f = 64hz, t a = +25 ? c (note 3) 100 115 db (note 4) 77 ecg channel input referred noise bw = 0.05 C 150hz, g ch = 20x 0.77 v rms 4.6 v pp bw = 0.05 C 40hz, g ch = 20x (note 3) 0.46 1.0 v rms 3.1 6.6 v pp input leakage current t a = +25c -1 0.1 +1 na input impedance (ina) common-mode, dc 45 g differential, dc 1500 m note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics electrical characteristics maxim integrated 3 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
(v dvdd = v avdd = +1.1v to +2.0v, v ovdd = +1.65v to +3.6v, f fclk = 32.768khz, ln_bioz = 1, t a = t min to t max , unless otherwise noted. typical values are at v dvdd = v avdd = +1.8v, v ovdd = +2.5v, t a = +25c.) (note 2) parameter symbol conditions min typ max units ecg channel total harmonic distortion thd v avdd = +1.80 v , v in = 65mv pp , f in = 64hz, g ch = 20x , electrod e o f fse t = 300mv 0.025 % v avdd = +1.1 v , v in = 30mv pp , f in = 64hz, g ch = 20x, electrode o f fset = 300mv 0.3 ecg channel gain setting g ch programmable, see register map 20 to 160 v/v ecg channel gain error (excluding reference) v avdd = +1.8 v , g ch = 20x, ecgp = ecgn = vmid -2.5 +2.5 % v avdd = +1.1 v , g ch = 20x, ecgp = ecgn = vmid -4.5 +4.5 % ecg channel offset error (note 5) 0.1 % of fsr adc resolution 18 bits adc sample rate programmable, see register map 125 to 512 sps capp to capn impedance r hpf fhp = 1/(2 x r hpf x c hpf ), c hpf = capacitance between capp and capn 320 450 600 k analog high-pass filter slew current fast recovery enabled (1.8v) 160 a fast recovery enabled (1.1v) 55 fast recovery disabled 0.09 fast settling recovery time c hpf = 10 f , note: varies by sample rate, see t able 3. 500 ms digital low-pass filter linear phase fir flter. dlpf[0:1] = 01 40 hz dlpf[0:1] = 10 100 dlpf[0:1] = 11 150 digital high-pass filter phase-corrected 1st-order iir flter. dhpf = 1 0.5 hz ecg power supply rejection psrr lead bias disabled, dc 107 db lead bias disabled, f sw = 64hz 110 electrical characteristics (continued) maxim integrated 4 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
(v dvdd = v avdd = +1.1v to +2.0v, v ovdd = +1.65v to +3.6v, f fclk = 32.768khz, ln_bioz = 1, t a = t min to t max , unless otherwise noted. typical values are at v dvdd = v avdd = +1.8v, v ovdd = +2.5v, t a = +25c.) (note 2) parameter symbol conditions min typ max units ecg input mux dc lead off check pullup/ pulldown imag[2:0] = 001 5 na imag[2:0] = 010 10 imag[2:0] = 011 20 imag[2:0] = 100 50 imag[2:0] = 101 100 dc lead off comparator low threshold vth[1:0] = 11 (note 6) v mid C 0.50 v vth[1:0] = 10 (note 7) v mid C 0.45 vth[1:0] = 01 (note 8) v mid C 0.40 vth[1:0] = 00 v mid C 0.30 dc lead off comparator high threshold vth[1:0] = 11 (note 6) v mid + 0.50 v vth[1:0] = 10 (note 7) v mid + 0.45 vth[1:0] = 01 (note 8) v mid + 0.40 vth[1:0] = 00 v mid + 0.30 lead bias impedance lead bias enabled rbiasv[1:0] = 00 50 m rbiasv[1:0] = 01 100 rbiasv[1:0] = 10 200 lead bias voltage v mid lead bias enabled v avdd / 2.15 v calibration voltage magnitude single-ended v mag = 0 0.25 mv v mag = 1 0.50 calibration voltage magnitude error single-ended (note 9) -3 +3 % calibration voltage frequency programmable, see register map 0.0156 to 256 hz calibration voltage pulse time programmable, see register map fifty = 0 0.03052 to 62.474 ms fifty = 1 50 % electrical characteristics (continued) maxim integrated 5 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
(v dvdd = v avdd = +1.1v to +2.0v, v ovdd = +1.65v to +3.6v, f fclk = 32.768khz, ln_bioz = 1, t a = t min to t max , unless otherwise noted. typical values are at v dvdd = v avdd = +1.8v, v ovdd = +2.5v, t a = +25c.) (note 2) parameter symbol conditions min typ max units bioimpedance (bioz) channel signal generator resolution square wave generator 1 bits drvp/n injected full-scale current programmable, see register map 8 to 96 a pp drvp/n injected current accuracy internal bias resistor -30 +30 % external bias resistor (0.1%, 10ppm, 324k ) -10 +10 drvp/n injected current power supply rejection <1 %/v drvp/n injected current temperatue coeffcient external bias resistor, 32 a pp , 0 to 70oc (0.1%, 10ppm, 324k ) 50 ppm/c drvp/n compliance voltage v drvp - v drvn (v avdd - 0.5) v pp current injection frequency programmable, see register map 0.125 to 131.072 khz ac differential input range shift from nominal gain < 1% (1.1v) 25 mv shift from nominal gain < 1% (1.8v) 90 mv bioz channel gain programmable, see register map 10 to 80 v/v adc sample rate programmable, see register map 24.98 to 64 sps adc resolution 20 bits input referred noise (bip, bin) bw = 0.05 to 4hz, gain = 20x 0.16 v rms bw = 0.05 to 4hz, gain = 20x 1.1 v pp impedance resolution dc to 4hz, 32a pp , 40khz, gain = 20x, r body = 680 40 m pp input analog high pass filter programmable, see register map 125 to 7200 hz demodulation phase range programmable, see register map 0-180 demodulation phase resolution programmable, see register map 11.25 output digital low pass filter bioz_dlpf[1:0] = 01 4 hz bioz_dlpf[1:0] = 10 8 bioz_dlpf[1:0] = 11 16 output digital high pass filter bioz_dhpf[1:0] = 01 0.05 hz bioz_dhpf[1:0] = 1x 0.5 hz electrical characteristics (continued) maxim integrated 6 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
(v dvdd = v avdd = +1.1v to +2.0v, v ovdd = +1.65v to +3.6v, f fclk = 32.768khz, ln_bioz = 1, t a = t min to t max , unless otherwise noted. typical values are at v dvdd = v avdd = +1.8v, v ovdd = +2.5v, t a = +25c.) (note 2) parameter symbol conditions min typ max units bioimpedance (bioz) input mux dc lead off check imag[2:0] = 001 5 na imag[2:0] = 010 10 imag[2:0] = 011 20 imag[2:0] = 100 50 imag[2:0] = 101 100 dc lead off comparator low threshold dcloff_vth[1:0] = 11 (note 6) v mid C 0.50 v dcloff_vth[1:0] = 10 (note 7) v mid C 0.45 dcloff_vth[1:0] = 01 (note 8) v mid C 0.40 dcloff_vth[1:0] = 00 v mid C 0.30 dc lead off comparator high threshold dcloff_vth[1:0] = 11 (note 6) v mid + 0.50 v dcloff_vth[1:0] = 10 (note 7) v mid + 0.45 dcloff_vth[1:0] = 01 (note 8) v mid + 0.40 dcloff_vth[1:0] = 00 v mid + 0.30 lead bias impedance lead bias enabled, rbiasv[1:0] = 00 50 m lead bias enabled, rbiasv[1:0] = 01 100 lead bias enabled, rbiasv[1:0] = 10 200 lead bias voltage lead bias enabled. programmable, see register map v avdd / 2.15 v calibration voltage magnitude single-ended. v mag = 0 0.25 mv single-ended. v mag = 1 0.50 calibration voltage error single-ended. (note 9) -3 +3 % calibration voltage frequency programmable, see register map 0.0156 to 256 hz calibration voltage pulse time programmable, see register map cal_fifty = 0 0.03052 to 62.474 ms cal_fifty = 1 50 % resistive load nominal value r val programmable, see register map 0.625 to 5.0 k resistive load modulation value r mod programmable, see register map 15 to 2960 m resistive load modulation frequency f mod programmable, see register map 0.625 to 4.0 hz electrical characteristics (continued) maxim integrated 7 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
(v dvdd = v avdd = +1.1v to +2.0v, v ovdd = +1.65v to +3.6v, f fclk = 32.768khz, ln_bioz = 1, t a = t min to t max , unless otherwise noted. typical values are at v dvdd = v avdd = +1.8v, v ovdd = +2.5v, t a = +25c.) (note 2) parameter symbol conditions min typ max units pace detection pace artifact width programmable, see register map 0.05 to 2.0 ms minimum pace artifact amplitude 0.5 mv time resolution 16 s recovery time large pacer pulse (100mv to 700mv) 500 s aout output voltage swing f = 1khz, thd < 0.2% 100 mv pp internal reference/common-mode v bg output voltage v bg 0.650 v v bg output impedance 100 n external v bg compensation capacitor c vbg 1 f v ref output voltage v ref t a = +25oc 0.995 1.000 1.005 v v ref 7hpshudwxuh&rhiflhqw tc ref t a = 0oc to +70oc 10 ppm/oc v ref buffer line regulation 330 v/v v ref buffer load regulation i load = 0 to 100a 25 v/a external v ref compensation capacitor c ref 1 10 f vcm output voltage v cm 0.650 v external v cm compensation capacitor c cm 1 10 f digital inputs (sdi, sclk, csb, fclk) input-voltage high v ih 0.7 x v ovdd v input-voltage low v il 0.3 x v ovdd v input hysteresis v hys 0.05 x v ovdd v input capacitance c in 10 pf input current i in -1 +1 a digital outputs (sdo, intb, int2b) output voltage high v oh i source = 1ma v ovdd - 0.4 v output voltage low v ol i sink = 1ma 0.4 v three-state leakage current -1 +1 a three-state output capacitance 15 pf power supply analog supply voltage v avdd connect avdd to dvdd 1.1 2.0 v digital supply voltage v dvdd connect dvdd to avdd 1.1 2.0 v interface supply voltage v ovdd power for i/o drivers only 1.65 3.6 v electrical characteristics (continued) maxim integrated g 8 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
(v dvdd = v avdd = +1.1v to +2.0v, v ovdd = +1.65v to +3.6v, f fclk = 32.768khz, ln_bioz = 1, t a = t min to t max , unless otherwise noted. typical values are at v dvdd = v avdd = +1.8v, v ovdd = +2.5v, t a = +25c.) (note 2) parameter symbol conditions min typ max units supply current i avdd + i dvdd ecg channel v avdd = v dvdd = +1.1v 76 a v avdd = v dvdd = +1.8v 95 v avdd = v dvdd = +2.0v 102 120 ecg channel with pace (note 3) v avdd = v dvdd = +1.1v 100 v avdd = v dvdd = +1.8v 124 v avdd = v dvdd = +2.0v 133 150 ecg channel with pace and aout (note 3) v avdd = v dvdd = +1.1v 114 v avdd = v dvdd = +1.8v 138 v avdd = v dvdd = +2.0v 147 190 ecg channel with pace, and bioz, ln_bioz = 0 v avdd = v dvdd = +1.1v 205 v avdd = v dvdd = +1.8v 232 v avdd = v dvdd = +2.0v 242 270 ecg channel with pace, and bioz, ln_bioz = 1 v avdd = v dvdd = +1.1v 220 v avdd = v dvdd = +1.8v 247 v avdd = v dvdd = +2.0v 256 285 bioz channel , ln_bioz = 0 (note 3) v avdd = v dvdd = +1.1v 144 v avdd = v dvdd = +1.8v 163 v avdd = v dvdd = +2.0v 170 190 bioz channel , ln_bioz = 1 (note 3) v avdd = v dvdd = +1.1v 158 v avdd = v dvdd = +1.8v 178 v avdd = v dvdd = +2.0v 185 205 ecg channel and bioz, ln_bioz = 0 (note 3) v avdd = v dvdd = +1.1v 186 v avdd = v dvdd = +1.8v 211 v avdd = v dvdd = +2.0v 220 250 ecg channel and bioz, ln_bioz = 1 (note 3) v avdd = v dvdd = +1.1v 200 v avdd = v dvdd = +1.8v 225 v avdd = v dvdd = +2.0v 235 265 ulp lead on detect t a = +70oc 1.3 t a = +25oc 0.63 2.5 interface supply current i ovdd v ovdd = +1.65v, ecg channel at 512sps (note 10) 0.2 a v ovdd = 3.6v, ecg channel at 512sps (note 10) 0.6 1.6 shutdown current i savdd + i sdvdd v avdd = v dvdd = 2.0v (note 5) t a = +70oc 1.3 a t a = +25oc 0.58 2.5 i sovdd v ovdd = 3.6v, v avdd = v dvdd = 2.0v 1.1 esd protection ecgp, ecgn, bip, bin iec 61000-4-2 contact discharge (note 11) 8 kv iec 61000-4-2 air-gap discharge (note 11) 15 electrical characteristics (continued) maxim integrated 9 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
(v dvdd = v avdd = +1.1v to +2.0v, v ovdd = +1.65v to +3.6v, f fclk = 32.768khz, ln_bioz = 1, t a = t min to t max , unless otherwise noted. typical values are at v dvdd = v avdd = +1.8v, v ovdd = +2.5v, t a = +25c.) (note 2) note 2: all devices are 100% production tested at t a = +25oc. specifications over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. note 3: guaranteed by design and characterization. not tested in production. note 4: one electrode drive with <10 source impedance, the other driven with 51k in parallel with a 47nf per iec60601-2-47. note 5: inputs connected to 51k in parallel with a 47nf to v cm . note 6: use this setting only for v avdd = v dvdd 1.65v. note 7: use this setting only for v avdd = v dvdd 1.55v. note 8: use this setting only for v avdd = v dvdd 1.45v. note 9: this specification defines the accuracy of the calibration voltage source as applied to the ecg input, not as measured through the adc channel. note 10: f sclk = 4mhz, burst mode, efit = 8, c sdo = c intb = 50pf. note 11: esd test performed with 1k? series resistor designed to withstand 8kv surge voltage. parameter symbol conditions min typ max units timing characteristics (note 3) sclk frequency f sclk 0 12 mhz sclk period t cp 83 ns sclk pulse width high t ch 15 ns sclk pulse width low t cl 15 ns csb fall to sclk rise setup time t css0 to 1st sclk rising edge (re) 15 ns csb fall to sclk rise hold t ime t csh0 applies to inactive re preceding 1st re 0 ns csb rise to sclk rise hold time t csh1 applies to 32nd re, executed write 10 ns csb rise to sclk rise t csa applies to 32nd re, aborted write sequence 15 ns sclk rise to csb fall t csf applies to 32nd re 100 ns csb pulse-width high t cspw 20 ns sdi-to-sclk rise setup time t ds 8 ns sdi to sclk rise hold time t dh 8 ns sclk fall to sdo transition t dot c load = 20pf 40 ns c load = 20pf, v avdd = v dvdd 1.8v, v dvdd 2.5v 20 ns sclk fall to sdo hold t doh c load = 20pf 2 ns csb fall to sdo fall t doe enable time, c load = 20pf 30 ns csb rise to sdo hi-z t doz disable time 35 ns fclk frequency f fclk external reference clock 32.768 khz fclk period t fp 30.52 s fclk pulse-width high t fh 50% duty cycle assumed 15.26 s fclk pulse-width low t fl 50% duty cycle assumed 15.26 s timing characteristics (note 3) maxim integrated 10 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
figure 1a. spi timing diagram figure 1b. fclk timing diagram d o 23 t csh 1 t csf 1 2 3 4 5 6 7 8 31 a 5 a 6 a4 a3 a2 a1 a0 r/wb d in 1 d in 0 t ds t css0 sdi t csh0 32 1' t csa t cspw d o 1 t doe z z 9 10 d in 23 d in 22 d o 0 a6' d o 22 sclk csb sdo t dh t cp t ch t cl t dot t doh t doz t fp fclk t fh t fl maxim integrated 11 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
(v dvdd = v avdd = 1.8v, v ovdd = 2.5v, t a = +25c, unless otherwise noted.) typical operating characteristics -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 64 128 192 256 noise (db) frequency (hz) ecg noise spectrum vs. frequency inputs shorted, gain = 160, lpf = 150hz toc04 -250 -200 -150 -100 -50 0 0 8 16 24 32 noise (db) frequency (hz) bioz noise spectrum vs. frequency inputs shorted, gain = 10, lpf = 4hz toc05 -250 -200 -150 -100 -50 0 0 8 16 24 32 noise (db) frequency (hz) bioz noise spectrum vs. frequency inputs shorted, gain = 10, lpf = 16hz toc06 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 64 128 192 256 noise (db) frequency (hz) ecg noise spectrum vs. frequency inputs shorted, gain = 20, lpf = 40hz toc01 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 64 128 192 256 noise (db) frequency (hz) ecg noise spectrum vs. frequency inputs shorted, gain = 20, lpf = 150hz toc02 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 64 128 192 256 noise (db) frequency (hz) ecg noise spectrum vs. frequency inputs shorted, gain = 160, lpf = 40hz toc03 -250 -200 -150 -100 -50 0 0 8 16 24 32 noise (db) frequency (hz) bioz noise spectrum vs. frequency inputs shorted, gain = 80, lpf = 4hz toc07 -250 -200 -150 -100 -50 0 0 8 16 24 32 noise (db) frequency (hz) bioz noise spectrum vs. frequency inputs shorted, gain = 80, lpf = 16hz toc08 -4 -3 -2 -1 0 1 2 3 4 0 2 4 6 8 10 noise (v) time (s) ecg input - referred noise vs. time gain = 20, lpf = 40hz (10s) toc09 maxim integrated 12 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
(v dvdd = v avdd = 1.8v, v ovdd = 2.5v, t a = +25c, unless otherwise noted.) typical operating characteristics (continued) 0 200 400 600 800 1000 1200 1400 1600 1800 -50 -49 -48 -47 -46 -45 -44 -43 -42 number of occurrences adc code ecg noise histogram gain = 20, lpf = 40hz toc13 stdev = 0.47v offset = - 17.71v -4 -3 -2 -1 0 1 2 3 4 0 2 4 6 8 10 noise (v) time (s) ecg input - referred noise vs. time gain = 20, lpf = 150hz (10s) toc10 0 20 40 60 80 100 120 140 160 180 200 -72 -65 -58 -51 -44 -37 -30 -23 -16 -9 -2 5 12 19 number of occurrences adc code ecg noise histogram gain = 160, lpf = 150hz toc16 -4 -3 -2 -1 0 1 2 3 4 0 2 4 6 8 10 noise (v) time (s) ecg input - referred noise vs. time gain = 160, lpf = 40hz (10s) toc11 60 70 80 90 100 110 120 130 0 64 128 192 256 cmrr (db) frequency (hz) ecg cmrr vs. frequency ( mismatched load is 0 ? on ecgp, 51k ? || 47nf on ecgn) 0 ? on both inputs, gain = 20 toc17 51k ? || 47nf load on both inputs, gain = 20 mismatched inputs, gain = 160 mismatched inputs, gain = 20 51k ? || 47nf load on both inputs, gain = 160 -4 -3 -2 -1 0 1 2 3 4 0 2 4 6 8 10 noise (v) time (s) ecg input - referred noise vs. time gain = 160, lpf = 150hz (10s) toc12 1 10 100 1000 0 0.5 1 1.5 2 2.5 psrr (lsb/v) frequency (mhz) ecg psrr vs. frequency toc18 0 100 200 300 400 500 600 700 800 900 1000 -54 -52 -50 -48 -46 -44 -42 -40 -38 number of occurrences adc code ecg noise histogram gain = 20, lpf = 150hz toc14 0 50 100 150 200 250 300 350 400 -45 -41 -37 -33 -29 -25 -21 -17 -13 -9 -5 -1 3 number of occurrences adc code ecg noise histogram gain = 160, lpf = 40hz toc15 maxim integrated g 13 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
(v dvdd = v avdd = 1.8v, v ovdd = 2.5v, t a = +25c, unless otherwise noted.) typical operating characteristics (continued) 1 10 100 1000 10000 100000 1000000 10000000 -400 -200 0 200 400 input resistance (m ?) v cm - v mid (mv) no lead bias ecg common - mode input resistance vs. voltage toc22 50m ? lead bias 100m ? lead bias 200m ? lead bias 1 10 100 1000 10000 0 10 20 30 40 50 60 70 input resistance (m ?) temperature ( c) no lead bias ecg differential input resistance vs. temperature toc23 50m ? lead bias 100m ? lead bias 200m ? lead bias 1 10 100 1000 10000 100000 1000000 0 10 20 30 40 50 60 70 input resistance (m ?) temperature ( c) no lead bias ecg common - mode input resistance vs. temperature toc24 50m ? lead bias 100m ? lead bias 200m ? lead bias 1 10 100 1000 10000 0 64 128 192 256 input resistance (m ?) frequency (hz) no lead bias ecg differential input resistance vs. frequency toc19 50m ? lead bias 100m ? lead bias 200m ? lead bias 1 10 100 1000 10000 0 64 128 192 256 input resistance (m ? ) frequency (hz) no lead bias ecg common - mode input resistance vs. frequency toc20 50m ? lead bias 100m ? lead bias 200m ? lead bias 1 10 100 1000 10000 -500 -300 -100 100 300 500 input resistance (m ?) v ecgp - v ecgn (mv) no lead bias ecg differential input resistance vs. voltage toc21 50m ? lead bias 100m ? lead bias 200m ? lead bias 10 100 1000 10000 100000 1000000 -800 -600 -400 -200 0 200 400 600 800 input resistance (m ?) v bip - v bin (mv) no lead bias bioz differential input resistance vs. voltage toc25 50m ? lead bias 100m ? lead bias 200m ? lead bias 10 100 1000 10000 100000 1000000 -600 -400 -200 0 200 400 600 input resistance (m ?) v cm - v mid (mv) no lead bias bioz common - mode input resistance vs. voltage toc26 50m ? lead bias 100m ? lead bias 200m ? lead bias -120 -100 -80 -60 -40 -20 0 0 64 128 192 256 thd (db) frequency (hz) ecg thd vs. frequency ecg gain = 40 toc27 ecg gain = 20 ecg gain = 80 ecg gain = 160 maxim integrated 14 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
(v dvdd = v avdd = 1.8v, v ovdd = 2.5v, t a = +25c, unless otherwise noted.) typical operating characteristics (continued) -120 -100 -80 -60 -40 -20 0 20 0.1 1 10 100 1000 gain (db) frequency (hz) ecg filter response hpf = 0.5hz, lpf = 100hz gain = 20v/v, sample rate = 512 toc31 c hpf = 10 f dhpf = 0.5hz dlpf = 100hz -120 -100 -80 -60 -40 -20 0 0 20 40 60 80 100 thd (db) amplitdue (mv pk - pk ) ecg thd vs. input amplitude ecg gain = 40 toc28 ecg gain = 20 ecg gain = 80 ecg gain = 160 0 20 40 60 80 100 120 0 10 20 30 40 50 60 70 shutdown current (a) temperature ( c) bioz drive current vs. temperature internal biasing 96 a toc34 80 a 64 a 48 a 32 a 16 a 8 a -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 64 128 192 256 magnitude (db) frequency (hz) ecg fft gain = 20, f in = 25hz, lpf bypassed toc29 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 shutdown current (a) temperature ( c) bioz drive current vs. temperature external biasing toc35 80 a 8 a 32 a -120 -100 -80 -60 -40 -20 0 20 0.1 1 10 100 1000 gain (db) frequency (hz) ecg filter response hpf = 0.5hz, lpf = 40hz gain = 20v/v, sample rate = 512 toc30 c hpf = 10 f 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 0 10 20 30 40 50 60 70 shutdown current (a) temperature ( c) dvdd shutdown current v dvdd = +2.0v toc36 v dvdd = +1.8v v dvdd = +1.1v -120 -100 -80 -60 -40 -20 0 20 0.1 1 10 100 1000 gain (db) frequency (hz) ecg filter response hpf = 0.5hz, lpf = 150hz gain = 20v/v, sample rate = 512 toc32 c hpf = 10 f dhpf = 0.5hz dlpf = 150hz 999.6 999.7 999.8 999.9 1000 1000.1 1000.2 1000.3 1000.4 1000.5 1000.6 0 10 20 30 40 50 60 70 vref (mv) temperature ( c) vref vs. temperature toc33 maxim integrated g 15 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
(v dvdd = v avdd = 1.8v, v ovdd = 2.5v, t a = +25c, unless otherwise noted.) typical operating characteristics (continued) 60 70 80 90 100 110 120 130 140 150 0 10 20 30 40 50 60 70 avdd and dvdd supply current (a) temperature ( c) avdd and dvdd supply current vs. temperature (ecg, pace enabled) 1.1v toc40 1.8v 2.0v 100 110 120 130 140 150 160 170 180 190 200 0 10 20 30 40 50 60 70 avdd and dvdd supply current (a) temperature ( c) avdd and dvdd supply current vs. temperature (bioz enabled, ln_bioz = 0) 1.1v toc41 1.8v 2.0v idrv = 32 a 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0 10 20 30 40 50 60 70 shutdown current (a) temperature ( c) avdd shutdown current v avdd = +2.0v toc37 v avdd = +1.8v v avdd = +1.1v v avdd = +1.5v 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0 10 20 30 40 50 60 70 shutdown current (a) temperature ( c) ovdd shutdown current v ovdd = +2.0v toc38 v ovdd = +1.8v v ovdd = +1.1v v ovdd = +1.5v 60 65 70 75 80 85 90 95 100 105 110 0 10 20 30 40 50 60 70 avdd and dvdd supply current (a) temperature ( c) avdd and dvdd supply current vs. temperature (ecg enabled) 1.1v toc39 1.8v 2.0v 160 170 180 190 200 210 220 230 240 250 260 0 10 20 30 40 50 60 70 avdd and dvdd supply current (a) temperature ( c) 1.1v toc42 1.8v 2.0v avdd and dvdd supply current vs. temperature (ecg, pace, bioz enabled, ln_bioz = 0) 1.1v 1.8v 2.0v idrv = 32 a maxim integrated g 16 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
(v dvdd = v avdd = 1.8v, v ovdd = 2.5v, t a = +25c, unless otherwise noted.) typical operating characteristics (continued) 0 0.2 0.4 0.6 0.8 1 1.2 0 10 20 30 40 50 60 70 avdd and dvdd ulp current (a) temperature ( c) avdd and dvdd ulp current vs. temperature 1.1v toc43 1.5v 2.0v 1.8v 1.8v -1.50 -1.00 -0.50 0.00 0.50 1.00 1.50 2.00 0 0.1 0.2 0.3 0.4 0.5 0.6 voltage (mv) time (s) ecg pacemaker pulse tolerance 2mv, 0.1ms pulse ecg signal toc47 2mv, 0.1ms pulse -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 0 0.1 0.2 0.3 0.4 0.5 0.6 voltage (mv) time (s) ecg pacemaker pulse tolerance 2mv, 2.0ms pulse ecg signal toc44 2mv, 2.0ms pulse -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 0 0.1 0.2 0.3 0.4 0.5 0.6 voltage (mv) time (s) ecg pacemaker pulse tolerance 200mv, 2.0ms pulse ecg signal toc45 200mv 2.0ms pulse -1.50 -1.00 -0.50 0.00 0.50 1.00 1.50 2.00 0 0.1 0.2 0.3 0.4 0.5 0.6 voltage (mv) time (s) ecg pacemaker pulse tolerance 20mv, 0.1ms pulse ecg signal toc46 20mv, 0.1ms pulse maxim integrated 17 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
bump pin name function wlp tqfn a1 1 drvp positive output current source for bio-impedance excitation. requires a series capacitor between pin and electrode. a2 2 drvn negative output current source for bio-impedance excitation. requires a series capacitor between pin and electrode. a3 4 bin bioimpedance negative input. a4 5 bip bioimpedance positive input. a5 6 ecgp ecg positive input. a6 7 ecgn ecg negative input. b1 27 vbg bandgap noise filter output. connect a 1.0f x7r ceramic capacitor between v bg and agnd. b2 26 rbias external resistor bias. connect a low tempco resistor between rbias and agnd. if external bias generator is not used then rbias can be left foating. b3, b4, c3, c4, d4 3, 8, 28 agnd analog power and reference ground. connect into the printed circuit board ground plane. b5 10 capn analog high-pass filter input. connect a 1f x7r capacitor (c hpf ) between capp and capn to form a 0.5hz high-pass response in the ecg channel. select a capaitor with a high voltage rating (25v) to improve linearity of the ecg signal path. MAX30001 tqfn (5mm x 5mm) *connect ep to agnd top view drvn bin bip ecgp ecgn drvp int2b sdo sdi intb sclk csb vcm rbias vbg dgnd cpll capn capp agnd ovdd agnd agnd + aout dvdd vref fclk avdd 14 8 9 10 11 12 13 22 28 27 26 25 24 23 15 16 17 18 19 20 21 7 6 5 4 3 2 1 *ep textop view (bump side down) a b c d wlp (2.7mm x 2.9mm) e drvp 1 drvn 2 bin 3 bip ecgp ecgn vbg rbias agnd agnd capn capp vcm aout agnd agnd dgnd cpll vref intb ovdd agnd fclk dvdd avdd int2b sdo sdi sclk csb 4 5 6 MAX30001 pin confgurations pin description maxim integrated 18 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
bump pin name function wlp tqfn b6 9 capp analog high-pass filter input. connect a 1f x7r capacitor (c hpf ) between capp and capn to form a 0.5hz high-pass response in the ecg channel. select a capaitor with a high voltage rating (25v) to improve linearity of the ecg signal path. c1 25 vcm common mode bu f fer output. connect a 10f x5r ceramic capacitor between v cm and agnd. c2 24 aout analog output voltage of the pace channel. programmable to select where in the signal path to output to aout. c5 12 digital ground for both digital core and i/o pad drivers. recommended to connect to agnd plane. c6 11 cpll pll loop filter input. connect 1nf capacitor between cpll and agnd. d1 23 vref adc reference bu f fer output. connect a 10f x5r ceramic capacitor between v ref and agnd. d2 21 intb interrupt output. intb is an active low status output. it can be used to interrupt an external device. d3 19 ov dd logic interface supply v oltage. d5 14 fclk external 32.768khz clock that controls the sampling of the internal sigma-delta converters and decimator. d6 13 dvdd digital core supply voltage. connect to avdd. e1 22 avdd analog core supply v oltage. connect to dvdd. e2 20 int2b interrupt 2 output. int2b is an active-low status output. it can be used to interrupt an external device. e3 18 sdo serial data output. sdo will change state on the falling edge of sclk when csb is lo w . sdo is three-stated when csb is high. e4 17 sdi serial data input. sdi is sampled into the device on the rising edge of sclk when csb is lo w . e5 16 sclk serial clock input. clocks data in and out of the serial interface when csb is lo w . e6 15 csb active-low chip-select input. enables the serial interface. exposed pad. connect ep to agnd. pin description (continued) maxim integrated 19 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
detailed description ecg channel figure 2 illustrates the ecg channel block diagram, excluding the adc. the channel comprises an input mux, a fast-recovering instrumentation amplifier, an anti- alias filter, and a programmable gain amplifier. the input mux includes several features such as esd protection, emi filtering, lead biasing, leads off checking, and ultra- low power leads-on checking. the output of this analog channel drives a high-resolution adc. input mux the ecg input mux shown in figure 3 contains integrated esd and emi protection, dc leads off detect current sources, lead-on detect, series isolation switches, lead biasing, and a programmable calibration voltage source to enable channel built in self-test. emi filtering and esd protection emi filtering of the ecgp and ecgn inputs consists of a single pole, low pass, differential, and common mode filter with the pole located at approximately 2mhz. the ecgp and ecgn inputs also have input clamps that protect the inputs from esd events. 8kv using the contact discharge method specifed in iec61000-4-2 esd 15kv using the air gap discharge method specifed in iec61000-4-2 esd for iec61000-4-2 esd protection, use 1k? series resistors on ecgp and ecgn that is rated to withstand 8kv surge voltages. figure 2. ecg channel input amplifier and pga excluding the adc fast settling esd, emi, input mux, dc lead check input amp aaf f -3db = 600hz -40db/dec ecgp ecgn capp capn pga MAX30001 c hpf maxim integrated 20 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
figure 3. ecg input mux av dd agnd av dd agnd dc lead-off check esd protection and emi filter av dd agnd 5m? 15m? ulp lead-on check v mid v mid lead bias 50, 100, 200m? 50, 100, 200m? av dd agnd calibration voltage agnd agnd agnd agnd agnd agnd 5-100na 5-100na 5-100na ecgp ecgn to ecg ina in+ to ecg ina in- v thh v thl v thh v thl 0.25, 0.5mv, uni, bipolar, 1/64 C 256hz, time high 0.25, 0.5mv, uni, bipolar, 1/64 C 256hz, duty cycle 5-100na agnd av dd 3r r input and polarity switches MAX30001 maxim integrated 21 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
dc leads-off detection and ulp leads-on detection the input mux leads-off detect circuitry consists of programmable sink/source dc current sources that allow for dc leads-off detection, while the channel is powered up in normal operation and an ultra-low-power (ulp) leads-on detect while the channel is powered-down. the MAX30001 accomplishes dc leads-off detection by applying a dc current to pull the ecg input voltage up to above v mid + v th or down to below v mid - v th . the current sources have user selectable values of 0na, 5na, 10na, 20na, 50na, and 100na that allow coverage of dry and wet electrode impedance ranges. supported thresholds are v mid 300mv (recommended), v mid 400mv, v mid 450mv, and v mid 500mv. a threshold of 400mv, 450mv, and 500mv must only be used when v avdd 1.45v, 1.55v, and 1.65v, respectively. a dynamic comparator protects against false flags generated by the input amplifier and input chopping. the comparator checks for a minimum continuous violation (or threshold exceeded) of 115ms to 140ms depending on the setting of fmstr[1:0] before asserting any one of the ldoff_xx interrupt flags ( figure 4 ). see registers cnfg_gen (0x10) and cnfg_emux (0x14) for configuration settings and see table 1 for recommended values given electrode type and supply voltage. the ulp lead on detect operates by pulling ecgn low with a pulldown resistance larger than 5m? and pulling ecgp high with a pullup resistance larger than 15m?. a low-power comparator determines if ecgp is pulled below a predefined threshold that occurs when both electrodes make contact with the body. when the impedance between ecgp and ecgn is less than 20m?, an interrupt lonint is asserted, alerting the c to a leads-on condition. a 0na/v mid 300mv selection is available allowing monitoring of the input compliance of the ina during non- dc lead-off checks. lead bias the MAX30001 limits the ecgp and ecgn dc input common mode range to v mid 150mv. this range can be maintained either through external or internal lead- biasing. internal dc lead-biasing consists of 50m?, 100m?, or 200m? selectable resistors to v mid that drive the electrodes within the input common mode requirements of the ecg channel and can drive the connected body to the proper common mode voltage level. see register cnfg_gen (0x10) to select a configuration. the common-mode voltage, v cm , can optionally be used as a body bias to drive the body to the common-mode voltage by connecting v cm to a separate electrode on the body through a high value resistor such as 1m to limit current into the body. if this is utilized then the internal lead bias resistors to v mid can be disabled. isolation and polarity switches the series switches in the MAX30001 isolate the ecgp and ecgn pins from the internal signal path, isolating it from the subject being monitored. the series switches are disabled by default. they must be enabled to record ecg. there are also polarity switches that will swap the inputs so that ecgp goes to the minus ina input and ecgn goes to the plus ina input. calibration voltage sources calibration voltage sources are available to provide 0.25mv (0.5mv pp ) or 0.5mv (1.0mv pp ) inputs to the ecg channel with programmable frequency and duty cycle. the sources can be unipolar/bipolar relative to v mid . figure 5 illustrates the possible calibration waveforms. frequency selections are available in 4x increments from 15.625mhz to 256hz with selected pulse widths varying from 30.5s to 31.723ms and 50% duty cycle. signals can be single-ended, differential, or common mode. this flexibility allows end-to-end channel-testing of the ecg signal path. when applying calibration voltage sources with the device connected to a subject, the series input switches must be disconnected so as not to drive signals into the subject. see registers cnfg_cal (0x12) and cnfg_emux (0x14) to select configuration. figure 4. lead off detect behavior v dd v mid vss ecgp,n vth_h vth_l intb >115ms ldoff_*h bits asserted above threshold below threshold <115ms maxim integrated 22 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
table 1. recommended lead bias, current source values, and thresholds for electrode impedance figure 5. calibration voltage source options i dc v th electrode impedance <100k 100k C 200k 200k C 400k 400k C 1m 1m C 2m 2m C 4m 4m C 10m 10m C 20m i dc = 10na all settings of r b v th = v mid 300mv, 400mv i dc = 20na all settings of r b all settings of v th all settings of r b v th =v mid 400mv, 450mv, 500mv i dc = 50na all settings of r b all settings of v th all settings of r b v th =v mid 450mv, 500mv i dc = 100na all settings of r b all settings of v th all settings of r b v th =v mid 400mv, 450mv, 500mv calibration voltage source options v mid + 0 . 50 mv cal _ vmode = 0 cal _ vmag = 0 cal _ vmode = 1 cal _ vmag = 0 v mid v mid + 0 . 25 mv v mid - 0 . 25 mv v mid v mid + 0 . 25 mv v mid - 0 . 25 mv cal _ vmode = 0 cal _ vmag = 1 cal _ vmode = 1 cal _ vmag = 1 v mid v mid + 0 . 50 mv v mid - 0 . 50 mv v mid v mid - 0 . 50 mv t high t cal vcalp vcaln maim integrated 23 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
gain settings, input range, and filtering the devices ecg channel contains an input instru - mentation amplifier that provides low-noise, fixed-gain amplification (gain of 20) of the differential signal, rejects differential dc voltage due to electrode polarization, rejects common-mode interference primarily due to ac mains interference, and provides high input impedance to guarantee high cmrr even in the presence of severe electrode impedance mismatch (see figure 2 ). the differ - ential dc rejection corner frequency is set by an external capacitor (c hpf ) placed between pins capp and capn, refer to table 2 for appropriate value selection. there are three recommended options for the cutoff frequency: 5hz, 0.5hz, and 0.05hz. setting the cutoff frequency to 5hz provides the most motion artifact rejection at the expense of ecg waveform quality, making it best suited for heart rate monitoring. for ambulatory applications requiring more robust ecg waveforms with moderate motion artifact rejection, 0.5hz is recommended. select 0.05hz for patient monitoring applications in which ecg wave - form quality is the primary concern and poor rejection of motion artifacts can be tolerated. the high-pass corner frequency is calculated by the following equation: 1/(2 x r hpf x c hpf ) r hpf is specified in the electrical characteristics table. following the instrumentation amplifier is a 2-pole active anti-aliasing filter with a 600hz -3db frequency that pro - vides 57db of attenuation at half the modulator sampling rate (approximately 16khz) and a pga with programma - ble gains of 1, 2, 4, and 8v/v for an overall gain of 20, 40, 80, and 160v/v. the instrumentation amplifier and pga are chopped to minimize offset and 1/f noise. gain set - tings are configured via the cnfg_ecg (0x15) register. the useable common-mode range is v mid 150mv, inter - nal lead biasing can be used to meet this requirement. the useable dc differential range is 300mv to allow for electrode polarization voltages on each electrode. the input ac differential range is 32.5mv or 65mv pp . fast recovery mode the input instrumentation amplifier has the ability to rapidly recover from an excessive overdrive event such as a defibrillation pulse, high-voltage external pacing, and electro-surgery interference. there are two modes of recovery that can be used: automatic or manual recovery. the mode is programmed by the fast[1:0] bits in the mngr_dyn (0x05) register. table 2. ecg analog hpf corner frequency selection table 3. fast recovery mode recovery time vs. number of samples c hpf hpf corner frequency 0.1f 5hz 1.0f 0.5hz 10f 0.05hz sample rate (sps) number of samples recovery time (approximate) (ms) 512 255 498 256 127 496 128 63 492 500 249 498 250 124 496 125 64 512 200 99 495 199.8 99 495.5 maxim integrated 24 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
automatic mode engages once the saturation counter exceeds approximately 125ms (t sat ). the counter is activated the first time the adc output exceeds the sym - metrical threshold defined by the fast_th[5:0] bits in the mngr_dyn (0x05) register and accumulates the time that the adc output exceeds either the positive or nega - tive threshold. if the saturation counter exceeds 125ms, it triggers the fast settling mode (if enabled) and resets. the saturation counter can also be reset prior to trigger - ing the fast settling mode if the adc output falls below the threshold continuously for 125ms (t blw ). this feature is designed to avoid false triggers due to the qrs complex. once triggered, fast settling mode will be engaged for 500ms, see figure 6 . ecg samples are tagged if they were taken while fast settling mode was asserted. in manual mode, a user algorithm running on the host microcontroller or an external stimulus input will gener - ate the trigger to enter fast recovery mode. the host microcontroller then enables the manual fast recovery mode in the mngr_dyn (0x05) register. the manual fast recovery mode can be of a much shorter duration than the automatic mode and allows for more rapid recovery. one such example is recovery from external high-voltage pac - ing signals in a few milliseconds to allow the observation of a subsequent p-wave. figure 6. automatic fast settling behavior ecg v dd fast settling fast normal normal etag t blw 125ms v mid v ss enabled disabled disabled counter start stop reset start reset t sat 125ms v sat_thh v sat_thl t fast maxim integrated 25 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
decimation filter the decimation filter consists of an fir decimation filter to the data rate followed by a programmable iir and fir filter to implement hpf and lpf selections. the high-pass filter options include a 1st-order iir butterworth filter with a 0.4hz corner frequency along with a pass through setting for dc coupling. low-pass filter options include a 12-tap linear phase (constant group delay) fir filter with 40hz, 100hz, or 150hz corner fre - quencies. see register cnfg_ ecg (0x15) to configure the filters. table 4 illustrates the ecg latency in samples and time for each adc data rate. noise measurements table 5 shows the noise performance of the ecg channel of MAX30001 referred to the ecg inputs. table 4. ecg latency in samples and time as a function of ecg data rate and decimation table 5. ecg channel noise performance ecg channel settings latency input sample rate (hz) output data rate (sps) decimation ratio without lpf (input samples) with lpf (input samples) without lpf (ms) with lpf (ms) 32,768 512 64 650 1,034 19.836 31.555 32,000 500 64 650 1,034 20.313 32.313 32,768 256 128 2,922 3,690 89.172 1 12.610 32,000 250 128 2,922 3,690 91.313 1 15.313 32,000 200 160 1,242 2,202 38.813 68.813 31,968 199.8 160 1,242 2,202 38.851 68.881 32,768 128 256 3,370 4,906 102.844 149.719 32,000 125 256 3,370 4,906 105.313 153.313 gain bandwidth noise snr enob v/v hz v rms v pp db bits 20 40 0.46 3.04 97.7 15.9 100 0.64 4.20 94.9 15.5 150 0.77 4.60 93.2 15.2 40 40 0.40 2.64 92.9 15.1 100 0.54 3.56 90.3 14.7 150 0.66 4.34 88.6 14.4 80 40 0.35 2.31 88.0 14.3 100 0.50 3.33 84.9 13.8 150 0.62 4.09 83.1 13.5 160 40 0.34 2.22 82.4 13.4 100 0.49 3.24 79.1 12.8 150 0.61 4.01 77.2 12.5 maxim integrated 26 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
r-to-r detection the MAX30001 contains built-in hardware to detect r-r intervals using an adaptation of the pan-tompkins qrs detection algorithm*. the timing resolution of the r-r interval is approximately 8ms and depends on the set - ting of fmstr [1:0] in cnfg_gen (0x10) register. see table 26 for the timing resolution of each setting. when an r event is identified, the rrint status bit is asserted and the rtor_reg (0x25) register is updated with the count seen since the last r event. figure 7 illustrates the r-r interval on a qrs complex. refer to registers cnfg_rtor1 (0x1d) and cnfg_rtor2 (0x1e) for selection details. the latency of the r-to-r value written to the rtor interval memory register is the sum of the r-to-r deci - mation delay and the r-to-r detection delay blocks. the r-to-r decimation factor is fixed at 256 and the decima - tion delay (t r2r_dec ) is always 3,370 fmstr clocks, as shown in table 6 . the detection circuit consists of several digital filters and signal processing delays. these depend on the wndw[3:0] bits in the cnfg_rtor (0x1d) register. the detection delay (t r2r_det ) is described by the following equation: t r2r_det = 5,376 + 256 x wndw in fmstr clocks where wndw is an integer from 0 to 15 and the total latency (t r2r_del ) is the sum of the two delays and summarized in the equation below: t r2r_del = t r2r_dec + t r2r_det = 3,370 + 5,376 + 256 x wndw in fmstr clocks where wndw is an inte - ger from 0 to 15. the total r-to-r latency minus the ecg latency is the delay of the r-to-r value relative to the ecg data and can be used to place the first r-to-r value on the ecg data plot. the succeeding values in the r-to-r interval memory register can be used as is to locate subsequent r-to-r values on the ecg data plot relative to the initial placement. table 6. r-to-r decimation delay vs. register settings figure 7. r-to-r interval illustration * j. pan and w.j. tompkins, a real-time qrs detection algorithm, ieee trans. biomed. eng., vol. 32, pp. 230-236 fmstr [1:0] fmstr freq fmstr freq (hz) decimation rtor time resolution (ms) delay in r-to-r decimation fmstr clks (ms) 00 fclk 32,768 256 7.8125 3370 102.844 01 fclk x 625/640 32,000 256 8.0 3370 105.313 10 fclk x 625/640 32,000 256 8.0 3370 105.313 11 fclk x 640/656 31,968.78 256 8.0078 3370 105.415 r - r i n t e r v a l maim integrated 27 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
pace channel MAX30001 provides an analog based pace detection for up to three chamber pacing with data logging and ecg tagging for up to three rising and falling edges per ecg sample. see register cnfg_pace (0x1a) to select con - figuration and ecg fifo and pace memory for detailed descriptions of the ecg and pace fifos. real time monitoring of pace edge events can be accom - plished by unmasking pedge via en_int (0x02) and en_int2 (0x03) and using the self-clear behavior; see clr_pedge=1 in register mngr_int (0x04). current injection rates for bio-impedance measurements are limited to 40khz and 80khz when pace detection is enabled to avoid glitches caused by current injection being interpreted as a pace event. a single-ended analog signal is provided at pin aout to allow digitization of the pace pulses with an external analog to digital converter. see register cnfg_pace (0x1a) for gain, low pass and high pass filter options and aout signal selection. bioz channel figure 8 illustrates the bioz channel block diagram, excluding the adc. the channel comprises an input mux, an instrumentation amplifier, a mixer, an anti-alias filter, and a programmable gain amplifier. the mux includes several features such as esd protection, emi filtering, lead biasing, leads off checking, and ultra-low power leads-on checking. the output of this analog chan - nel drives a high-resolution adc. figure 8. bioz channel input amplifier, mixer, and pga excluding the adc and current drive output esd , emi, input mux, dc lead check input amp aaf bip bin drvp drvn pga push/pull current source hpf -20db/dec f -3db =600hz -40db/dec selectable phase MAX30001 pcb to pace channel maxim integrated 28 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
input mux the bioz input mux shown in figure 9 contains integrated esd and emi protection, dc leads off detect current sources and comparators, lead-on detect, series isolation switches, lead biasing, a programmable calibration voltage source to enable channel built in self-test for the pace channel, and a built in programmable resistor load. emi filtering and esd protection emi filtering of the bip and bin inputs consists of a single pole, low pass, differential, and common mode filter with the pole located at approximately 2mhz. the bip and bin inputs also have input clamps that protect the inputs from esd events. 8kv using the contact discharge method specifed in iec61000-4-2 esd 15kv using the air gap discharge method specifed in iec61000-4-2 esd for iec61000-4-2 esd protection, use 1k? series resistors on bip and bin that is rated to withstand 8kv surge voltages figure 9. bioz input mux av dd agnd av dd agnd dc lead-off check esd protection and emi filter av dd agnd 5m? 15m? ulp lead-on check v mid v mid lead bias 50, 100, 200m? 50, 100, 200m? av dd agnd calibration voltage agnd agnd agnd agnd agnd agnd 5-100na 5-100na 5-100na bip bin to bioz ina in+ to bioz ina in- v thh v thl v thh v thl 0.25, 0.5mv, uni, bipolar, 1/64 C 256hz, time high 0.25, 0.5mv, uni, bipolar, 1/64 C 256hz, duty cycle 5-100na agnd av dd 3r r input and r load switches MAX30001 esd protection agnd agnd agnd agnd drvp drvn programmable resistor load from drvp current generator from drvn current generator maxim integrated 29 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
leads-off detection and ulp leads-on detection MAX30001 provides the capability of detecting lead off scenarios that involve two electrode and four electrode configurations through the use of digital threshold and analog threshold comparisons. there are three methods to detect lead-off for the bioz channel. there is a com - pliance monitor for the current generator on the drvp and drvn pins detecting when the voltage on the pins is outside its operating range. the bioz_cgmon bit in the cnfg_bioz (0x18) register enables this function and the bcgmon, bcgmp, and bcgmn bits in the status (0x01) register indicate if the drvp and drvn pins are out of compliance. there is a dc lead-off circuit on the bip and bin pins (same as on the ecgp and ecgn pins, see ecg description) that sinks or sources a programmable dc current and window comparators with a programmable threshold to detect the condition. there is a digital lead off detection monitoring the output of the bioz adc with programmable under and overvoltage levels performing a digital comparison. the en_bloff bit in the cnfg_gen (0x10) register enables this function and the bloff_hi_it[7:0] and bloff_lo_ it[7:0] bits in the mngr_dyn (0x05) register sets the digital threshold for detection. refer to table 7 for lead off conditions and register settings to allow detection. the ulp lead-on detect operates by pulling bin low with a pulldown resistance larger than 5m? and pulling bip high with a pullup resistance larger than 15m?. a low- power comparator determines if bip is pulled below a predefined threshold that occurs when both electrodes make contact with the body. when the impedance between bip and bin is less than 20m?, an interrupt lonint is asserted, alerting the c to a leads-on condition. a 0na/v mid 300mv selection is available allowing monitoring of the input compliance of the ina during non- dc lead-off checks. lead bias the MAX30001 limits the bip and bin dc input common mode range to v mid 150mv. this range can be main - tained either through external/internal lead-biasing. internal dc lead-biasing consists of 50m?, 100m?, or 200m? selectable resistors to v mid that drive the electrodes within the input common mode requirements of the ecg channel and can drive the connected body to the proper common mode voltage level. see the en_ rbias[1:0], rbiasv[1:0], rbiasp, and rbiasn bits in the cnfg_gen (0x10) register to select a configuration. table 7. bioz lead off detection configurations configuration condition drvp/n bip/n measured signal register setting to detect two-electrode (shared drv/bi) 1 electrode off rail to rail rail to rail rail to rail (saturated inputs) cnfg_gen (0x10), en_bloff[1:0] = 10 or 11 mngr_dyn (0x05), bloff_hi_it[7:0] four-electrode (force/sense) 1 drv electrode off, large body coupling rail to rail normal ? signal cnfg_bioz (0x18), bioz_cgmon=1 1 drv electrode off, small body coupling rail to rail rail to rail rail to rail (saturated inputs) cnfg_gen (0x10), en_bloff[1:0] = 10 or 11 mngr_dyn (0x05), bloff_hi_it[7:0] 1 bi (sense) electrode off normal floating ? signal cnfg_gen (0x10), en_dcloff=10 both bip/n (sense) electrodes off normal floating no signal cnfg_gen (0x10), en_bloff[1:0] = 01 or 11 mngr_dyn (0x05), bloff_lo_it[7:0] 1 drv and 1 bi electrode off rail to rail wide swing, dependent on body coupling rail to rail cnfg_gen (0x10), en_bloff[1:0] = 10 or 11 mngr_dyn (0x05), bloff_hi_it[7:0] maxim integrated 30 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
the common-mode voltage, v cm , can optionally be used as a body bias to drive the body to the common-mode voltage by connecting v cm to a separate electrode on the body through a high value resistor such as 1m to limit curent into the body. if this is utilized then the internal lead bias resistors to v mid can be disabled. if ecgp/ecgn pins are shared with the bip/bin pins then it is only neces - sary to enable lead bias on ecg or bioz. calibration voltage sources calibration voltage sources are available to provide 0.25mv (0.5mv pp ) or 0.5mv (1.0mv pp ) inputs to the bioz/pace channel with programmable frequency and duty cycle. the sources can be unipolar/bipolar relative to v mid . figure 10 illustrates the possible calibration waveforms. frequency selections are available in 4x increments from 15.625mhz to 256hz with selected pulse widths varying from 30.5s to 31.723ms and 50% duty cycle. signals can be single-ended, differential, or common mode. this flexibility allows end-to-end channel-testing of the pace signal path and is primarily used for pacemaker pulse detection validation. when applying calibration voltage sources with the device connected to a subject, the series input switches must be disconnected so as not to drive signals into the subject. see registers cnfg_cal (0x12) and cnfg_bmux (0x14) to select configuration. figure 11. programmable resistive load topology figure 10. calibration voltage source options drvp _ int 5 k ? 10 k ? 2 . 5 k? 1 . 25 k ? 10 k ? 10 k ? 10 k ? 10 k ? 45 ? 9 . 65 k? 150 ? 100 ? 55 ? drvn _ int r val < 0 > r val < 1 > r val < 2 > r mod < 0 > r mod < 1 > r mod < 2 > r mod < 3 > calibration voltage source options v mid + 0 . 50 mv cal _ vmode = 0 cal _ vmag = 0 cal _ vmode = 1 cal _ vmag = 0 v mid v mid + 0 . 25 mv v mid - 0 . 25 mv v mid v mid + 0 . 25 mv v mid - 0 . 25 mv cal _ vmode = 0 cal _ vmag = 1 cal _ vmode = 1 cal _ vmag = 1 v mid v mid + 0 . 50 mv v mid - 0 . 50 mv v mid v mid - 0 . 50 mv t high t cal vcalp vcaln maxim integrated 31 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
programmable resistive load the programmable resistive load on the drvp/drvn pins allows a built in self-test of the current generator (cg) and the entire bioz channel. refer to figure 11 for implementation details. nominal resistance can be varied between 5k? and 625?. the modulation resistance is dependent on the nominal resistance value with resolution of 50.4m? to 2.96? at the largest nominal resistance (5k?) and 15.3m? to 46.3m? with the smallest nominal resistance (625?). refer to table 8 for a complete listing of nominal and modulated resistor values. modulation rate can be programmed between 625mhz to 4hz. see registers cnfg_cal (0x12) and cnfg_bmux (0x17) to select configuration for modulation rate and resistor value. current generator the current generator provides square-wave modulating differential current that is ac injected into the body via pins drvp and drvn with the bio-impedance sensed differentially through pins bip and bin. two and four electrode configurations are supported for typical wet and dry electrode impedances. table 8. programmable resistive load values r nom () r mod (m) r val r mod <2> <1> <0> <3> <2> <1> <0> 5000.000 - 0 0 0 0 0 0 0 2960.7 0 0 0 0 0 0 1 980.6 0 0 0 0 0 1 0 247.5 0 0 0 0 1 0 0 2500.000 - 0 0 1 0 0 0 0 740.4 0 0 1 0 0 0 1 245.2 0 0 1 0 0 1 0 61.9 0 0 1 0 1 0 0 1666.667 - 0 1 0 0 0 0 0 329.1 0 1 0 0 0 0 1 109.0 0 1 0 0 0 1 0 27.5 0 1 0 0 1 0 0 1250.000 - 0 1 1 0 0 0 0 185.1 0 1 1 0 0 0 1 61.3 0 1 1 0 0 1 0 1000.000 - 1 0 0 0 0 0 0 118.5 1 0 0 0 0 0 1 39.2 1 0 0 0 0 1 0 833.333 - 1 0 1 0 0 0 0 82.3 1 0 1 0 0 0 1 27.2 1 0 1 0 0 1 0 714.286 - 1 1 0 0 0 0 0 60.5 1 1 0 0 0 0 1 20.0 1 1 0 0 0 1 0 625.000 - 1 1 1 0 0 0 0 46.3 1 1 1 0 0 0 1 15.3 1 1 1 0 0 1 0 maxim integrated 32 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
current amplitudes between 8a pk to 96a pk are select - able with current injection frequencies between 128hz and 131.072khz in power of two increments. see register cnfg_bioz (0x18) for configuration selections. current amplitude should be chosen so as not exceed 90mv pp at the bip and bin pins based on the network impedance at the current injection frequency. a 47nf dc blocking capacitor is required between both drvp and drvn and their respective electrodes. current selection and resolution calculation example 1 (two terminal with common protection) selection of the appropriate current is accomplished by first calculating the network impedance at the injection frequency. worst case electrode impedances should be used. given figure 12 and a current injection frequency of 80khz, the network impedance is: e body p1 p2 s ee 2r r 2r 2r 2r 2.8k 1 jrc + + ++ =? + where r body 5 p1 n 5 p2 r s 5 e 0 & e = 5nf. the maximum cur - rent injection is the maximum ac input differential range (50mv pk glylghg e wkh qhwzrun lpshgdqfh n ru 17.8a pk . the closest selectable lower value is 16a pk . given the current injection value and the channel band - width (refer to register cnfg_bioz (0x18) for digital lpf selection) the resolvable impedance can be calculated by dividing the appropriate input referred noise by the current injection value. for example, with a bandwidth of 4hz, the input referred noise with a gain of 20v/v is 0.16v rms or 1.1v pp . the resolvable impedance is therefore 1.1v pp /16a pk p33rup rms . current selection and resolution calculation example 2 (four terminal) selection of the appropriate current is accomplished by first calculating the network impedance at the injection frequency. worst case electrode impedances should be used. given figure 13 and a current injection frequency of 80khz, the network impedance is: e body dp1 dp2 s ee 2r r 2r 2r 2r 2.7k 1 jrc + + ++ =? + where r body 5 dp1 n 5 dp2 r s 5 e 0& e = 5nf. the maximum current injection is the maximum drvp/n compliance voltage (v dd -0.5v = 0.6v for v dd = 1.1v) divided by the network lpshgdqfhnru pk . the closest selectable lower value is 96a pk . figure 12. example configuration C two terminal with common protection bip bin drvp drvn MAX30001 47pf 10pf physical electrodes 10pf pcb electrode models r body 100? c e = 5nf r s = 100? r e = 1m? c e = 5nf r s = 100? r e = 1m? 47nf 47nf defib protection r p1 r p2 200? 1k? r p1 r p2 200? 1k? maxim integrated g 33 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
given the current injection value and the channel band - width (refer to register cnfg_bioz (0x18) for digital lpf selection) the resolvable impedance can be calculated by dividing the appropriate input referred noise by the current injection value. for example, with a bandwidth of 4hz, the input referred noise with a gain of 40v/v is 0.12v rms or 0.78v pp . the resolvable impedance is therefore 0.78v pp /96a pk = 8m? pp or 1.2m? rms . decimation filter the decimation filter consists of an fir decimation filter to the data rate followed by a programmable iir and fir filter to implement hpf and lpf selections. the high-pass filter options include a fourth-order iir butterworth filter with a 0.05hz or 0.5hz corner frequency along with a pass through setting for dc coupling. lowpass filter options include a 12-tap linear phase (constant group delay) fir filter with 4hz, 8hz, or 16hz corner frequencies. see register cnfg_bioz (0x18) to configure the filters. table 9 illustrates the bioz latency in samples and time for each adc data rate. noise measurements table 10 shows the noise performance of the bioz channel of MAX30001 referred to the bioz inputs. reference and common mode buffer the MAX30001 features internally generated reference voltages. the bandgap output (v bg ) pin requires an external 1.0f capacitor to agnd and the reference output (v ref ) pin requires a 10f external capacitor to agnd for compensation and noise filtering. a common-mode buffer is provided to buffer 650mv which is used to drive common mode voltages for internal blocks. use a 10f external capacitor between v cm to agnd to provide compensation and noise filtering. the common-mode voltage, v cm , can optionally be used as a body bias to drive the body to the common-mode volt - age by connecting v cm to a separate electrode on the body through a high value resistor such as 1m?. if this is utilized then the internal lead bias resistors to v mid may be disabled if the input signals are within the common- mode input range. figure 13. example configurationfour terminal bip bin drvp drvn MAX30001 47pf 10pf physical electrodes 10pf pcb r body 100? c e = 5nf r s = 100? r e = 1m? c e = 5nf r s = 100? r e = 1m? 47nf 47nf c e = 5nf r s = 100? r e = 1m? c e = 5nf r s = 100? r e = 1m? electrode models r dp1 r dp2 defib protection 200? 1k? r bp1 r bp2 200? 1k? r bp1 r bp2 200? 1k? r dp1 r dp2 200? 1k? maxim integrated 34 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
snr = 20log(v in (rms)/v n (rms)), enob = (snr C 1.76)/6.02 v inpp = 100mv, v inrms = 35.4mv for a gain of 10v/v. the input amplitude is reduced accordingly for high gain settings. table 9. bioz latency in samples and time as a function of bioz data rate and decimation table 10. bioz channel noise performance bioz channel settings latency input sample rate (hz) output data rate (sps) decimation ratio without lpf (input samples) with lpf (input samples) without lpf(ms) with lpf (ms) 32,768 64 512 3,397 6,469 103.668 197.418 32,000 62.5 512 3,397 6,469 106.156 202.156 32,000 50 640 5,189 9,029 162.156 282.156 31,968 49.95 640 5,189 9,029 162.319 282.439 32,768 32 1,024 7,557 13,701 230.621 418.121 32,000 31.25 1,024 7,557 13,701 236.156 428.156 32,000 25 1,280 9,605 17,285 300.156 540.156 31,968 24.975 1,280 9,605 17,285 300.457 540.697 gain bandwidth noise snr enob v/v hz v rms v pp db bits 10 4 0.23 1.55 101.6 16.6 8 0.28 1.87 100.0 16.3 16 0.35 2.34 98.0 16.0 20 4 0.16 1.10 104.9 17.1 8 0.19 1.27 103.4 16.9 16 0.26 1.68 100.9 16.5 40 4 0.12 0.78 107.6 17.6 8 0.16 1.07 104.9 17.1 16 0.22 1.48 102.0 16.7 80 4 0.11 0.72 108.3 17.7 8 0.15 1.01 105.3 17.2 16 0.21 1.42 102.4 16.7 maxim integrated 35 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
spi interface description 32 bit normal mode read/write sequences the MAX30001 interface is spi/qspi/micro-wire/dsp compatible. the operation of the spi interface is shown in figure 1a. data is strobed into the MAX30001 on sclk rising edges. the device is programmed and accessed by a 32 cycle spi instruction framed by a csb low interval. the content of the spi operation consists of a one byte command word (comprised of a seven bit address and a read/write mode indicator, i.e., a[6:0] + r/ w ) followed by a three-byte data word. the MAX30001 is compatible with cpol = 0/cpha = 0 and cpol = 1/cpha = 1 modes of operation. write mode operations will be executed on the 32nd sclk rising edge using the first four bytes of data available. in write mode, any data supplied after the 32nd sclk rising edge will be ignored. subsequent writes require csb to de-assert high and then assert low for the next write com - mand. in order to abort a command sequence, the rise of csb must precede the updating (32nd) rising-edge of sclk, meeting the t csa requirement. read mode operations will access the requested data on the 8th sclk rising edge, and present the msb of the requested data on the following sclk falling edge, allowing the c to sample the data msb on the 9th sclk rising edge. configuration, status, and fifo data are all available via normal mode read back sequences. if more than 32 sclk rising edges are provided in a normal read sequence then the excess edges will be ignored and the device will read back zeros. if accessing the status register or the ecg, bioz or pace fifo memories, all interrupt updates will be made and the internal fifo read pointer will be incremented in response to the 30th sclk rising edge, allowing for inter - nal synchronization operations to occur. see the data tag structures used within each fifo for means of detecting end-of-file (eof) samples, invalid (empty samples) and other aides for efficiently using and managing normal mode read back operations. burst mode read sequence the MAX30001 provides commands to read back the ecg, bioz or pace fifo memory in a burst mode to increase data transfer efficiency. burst mode uses differ - ent register addresses than the normal read sequence register addresses. a modified burst mode is supported for each pace fifo word group (see description of pace0 to pace5 register group). the first 32 sclk cycles operate exactly as described for the normal mode. if the c continues to provide sclk edges beyond the 32nd rising edge, the msb of the next available fifo word will be presented on the next falling sclk edge, allowing the c to sample the msb of the next word on the 33rd sclk rising edge. any affected interrupts and/or fifo read pointers will be incremented in response to the (30+nx24)th sclk rising edge where n is an integer start - ing at 0. (i.e., on the 30th, 54th, and 78th sclk rising- edges for a three-word, burst-mode transfer). this mode of operation will continue for every 24 cycle sub frame, as long as there is valid data in the fifo. see the data tag structures used within each fifo for means of detecting end-of-file (eof) samples, invalid (empty samples) and other aides for efficiently using and manag - ing burst mode read back operations. there is no burst mode equivalent in write mode. maxim integrated 36 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
figure 14. spi normal mode transaction diagram figure 15. spi burst mode read transactions diagram 1 8 9 16 17 24 25 32 33 a 6 a 5 a 4 a 3 a 2 a 1 a 0 w d 23 d 16 d 15 d 8 d 7 d 0 command executed ignore d edges z z csb sdi sclk sdo spi normal mode write transaction 1 8 9 16 17 24 25 32 33 a 6 a 5 a 4 a 3 a 2 a 1 a 0 r interrupt / read pointer updated ( if applicable ) ignore d edges z csb sdi sclk sdo spi normal mode read transaction dont care dont care dont care dont care dont care d o 23 d o 16 d o 15 d o 8 d o 7 d o 0 30 1 8 9 16 17 24 25 32 a 6 a 5 a 4 a 3 a 2 a 1 a 0 r read pointer updated ( to b ) z csb sdi sclk sdo spi burst mode read transaction ( 3 fifo word example ) dont care dont care dont care d a 23 d a 16 d a 15 d a 8 d a 7 d a 0 33 40 41 48 49 56 d b 16 d b 15 d b 8 d b 7 d b 0 d b 23 d b 23 57 64 65 72 73 80 d c 16 d c 15 d c 8 d c 7 d c 0 d c 23 csb sclk sdo csb sclk sdo continued transaction ( sub - frame 2 ) continued transaction ( sub - frame 3 ) z d c 23 30 read pointer updated ( to c ) read pointer updated ( to d ) 54 78 maxim integrated 37 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
user command and register map reg [6:0] name r/w mode data index 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x00 no-op r/w x / x / x x / x / x x / x / x x / x / x x / x / x x / x / x x / x / x x / x / x 0x01 status r eint eovf fstint dclo ffint bint bovf bover bundr bcgmon pint povf pedge lonint rrint samp pllint x x bcgmp bcgmn ldoff_ph ldoff_pl ldoff_nh ldoff_nl 0x02 0x03 en_int en_int2 r/w en_eint en_eovf en_ fstint en_ dcloffint en_bint en_bovf en_bover en_bundr en_bcgmon en_pint en_povf en_pedge en_ lonint en_ rrint en_samp en_ pllint x x x x x x intb_type[1:0] 0x04 mngr_ int r/w efit[4:0] bfit[2:0] x x x x x x x x x clr_ fast clr_rrint[1:0] clr_pedge clr_ samp samp_it[1:0] 0x05 mngr_ dyn r/w fast[1:0] fast_th[5:0] bloff_hi_it[7:0] bloff_lo_it[7:0] 0x08 sw_rst w data required for execution = 0x000000 0x09 synch w data required for execution = 0x000000 0x0a fifo_ rst w data required for execution = 0x000000 0x0f info r 0 1 0 1 rev_id[3:0] x x 0 1 x x x x x x x x x x x x 0x10 cnfg_ gen r/w en_ulp_lon[1:0] fmstr[1:0] en_ecg en_bioz en_pace x en_bloff[1:0] en_dcloff[1:0] ipol imag[2:0] vth[1:0] en_rbias[1:0] rbiasv[1:0] rbiasp rbiasn 0x12 cnfg_ cal r/w x en_vcal vmode vmag x x x x x fcal[2:0] fifty thigh[10:8] thigh[7:0] 0x14 cnfg_ emux r/w ecg_pol x ecg_ openp ecg_ openn ecg_calp_sel[1:0] ecg_caln_sel[1:0] x x x x x x x x x x x x x x x x 0x15 cnfg_ ecg r/w ecg_rate[1:0] x x x x ecg_gain[1:0] x ecg_ dhpf ecg_dlpf[1:0] x x x x x x x x x x x x maxim integrated 38 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
user command and register map (continued) reg [6:0] name r/w mode data index 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x17 cnfg_ bmux r/w x x bmux_ openp bmux_ openn bmux_calp_sel[1:0] bmux_caln_sel[1:0] x x bmux_cg_mode[1:0] bmux_en_ bist bmux_rnom[2:0] x bmux_rmod[2:0] x x bmux_fbist[1:0] 0x18 cnfg_ bioz r/w bioz_rate bioz_ahpf[2:0] ext_rbias ln_bioz bioz_gain[1:0] bioz_dhpf[1:0] bioz_dlpf[1:0] bioz_fcgen[3:0] bioz_ cgmon bioz_cgmag[2:0] bioz_phoff[3:0] 0x1a cnfg_ pace r/w pace_pol x x x diff_off pace_gain[2:0] x aout_ lbw aout[1:0] x x x x pace_dacp[3:0] pace_dacn[3:0] 0x1d cnfg_ rtor1 r/w wndw[3:0] rgain[3:0] en_rtor x pavg[1:0] ptsf[3:0] x x x x x x x x 0x1e cnfg_ rtor2 r/w x x hoff[5:0] x x ravg[1:0] x rhsf[2:0] x x x x x x x x 0x20 ecg_ fifo_ burst r+ ecg fifo burst mode read back see fifo description for details 0x21 ecg_ fifo r ecg fifo normal mode read back see fifo description for details 0x22 bioz_ fifo_ burst r+ bioz fifo burst mode read back see fifo description for details 0x23 bioz_ fifo r bioz fifo normal mode read back see fifo description for details 0x25 rtor r r-to-r interval register read back see fifo description for details 0x30 pace0_ burst r pace0 (data sets 0 to 5) burst mode read back see pace description for details 0x31 pace0_a r pace0 (data sets 0 and 1) normal mode read back see pace description for details 0x32 pace0_b r pace0 (data sets 2 and 3) normal mode read back see pace description for details 0x33 pace0_c r pace0 (data sets 4 and 5) normal mode read back see pace description for details 0x34 pace1_ burst r pace1 (data sets 0 to 5) burst mode read back see pace description for details 0x35 pace1_a r pace1 (data sets 0 and 1) normal mode read back see pace description for details 0x36 pace1_b r pace1 (data sets 2 and 3) normal mode read back see pace description for details 0x37 pace1_c r pace1 (data sets 4 and 5) normal mode read back see pace description for details maxim integrated 39 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
user command and register map (continued) reg [6:0] name r/w mode data index 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x38 pace2_ burst r+ pace2 (data sets 0 to 5) burst mode read back see pace description for details 0x39 pace2_a r pace2 (data sets 0 and 1) normal mode read back see pace description for details 0x3a pace2_b r pace2 (data sets 2 and 3) normal mode read back see pace description for details 0x3b pace2_c r pace2 (data sets 4 and 5) normal mode read back see pace description for details 0x3c pace3_ burst r+ pace3 (data sets 0 to 5) burst mode read back see pace description for details 0x3d pace3_a r pace3 (data sets 0 and 1) normal mode read back see pace description for details 0x3e pace3_b r pace3 (data sets 2 and 3) normal mode read back see pace description for details 0x3f pace3_c r pace3 (data sets 4 and 5) normal mode read back see pace description for details 0x40 pace4_ burst r+ pace4 (data sets 0 to 5) burst mode read back see pace description for details 0x41 pace4_a r pace4 (data sets 0 and 1) normal mode read back see pace description for details 0x42 pace4_b r pace4 (data sets 2 and 3) normal mode read back see pace description for details 0x43 pace4_c r pace4 (data sets 4 and 5) normal mode read back see pace description for details 0x44 pace5_ burst r+ pace5 (data sets 0 to 5) burst mode read back see pace description for details 0x45 pace5_a r pace5 (data sets 0 and 1) normal mode read back see pace description for details 0x46 pace5_b r pace5 (data sets 2 and 3) normal mode read back see pace description for details 0x47 pace5_c r pace5 (data sets 4 and 5) normal mode read back see pace description for details 0x7f no-op r/w x/x/x x/x/x x/x/x x/x/x x/x/x x/x/x x/x/x x/x/x note: r/w mode r+ denotes burst mode. x = dont care maxim integrated 40 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
register description no_op (0x00 and 0x7f) registers no operation (no_op) registers are read-write registers that have no internal effect on the device. if these registers are read back, dout remains zero for the entire spi transaction. any attempt to write to these registers is ignored without impact to internal operation. status (0x01) register status is a read-only register that provides a comprehensive overview of the current status of the device. the first two bytes indicate the state of all interrupt bits (regardless of whether interrupts are enabled in registers en_int (0x02) or en_int2 (0x03)). all interrupt bits are active high. the last byte includes detailed status information for conditions associated with the other interrupt bits. table 11. status (0x01) register map table 12. status (0x01) register meaning reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x01 status r eint eovf fstint dcloff int bint bovf bover bundr bcgmon pint povf pedge lonint rrint samp pllint x x bcgmp bcgmn ldoff_ ph ldoff_ pl ldoff_ nh ldoff_ nl index name meaning d[23] eint ecg fifo interrupt. indicates that ecg records meeting/exceeding the ecg fifo interrupt threshold (efit) are available for readback. remains active until ecg fifo is read back to the extent required to clear the efit condition. d[22] eovf ecg fifo overfow. indicates that the ecg fifo has overfown and the data record has been corrupted. remains active until a fifo reset (recommended) or synch operation is issued. d[21] fstint ecg fast recovery mode. issued when the ecg fast recovery mode is engaged (either manually or automatically). status and interrupt clear behavior is defned by clr_f ast, see mngr_int for details. d[20] dcloffint dc lead-off detection interrupt. indicates that the MAX30001 has determined it is in an ecg leads off condition (as selected in cnfg_gen) for more than 90ms. remains active as long as the leads- off condition persists, then held until cleared by status read back (32nd sclk). d[19] bint bioz fifo interrupt. indicates bioz records meeting/exceeding the bioz fifo interrupt threshold (bfit) are available for read back. remains active until bioz fifo is read back to the extent required to clear the bfit condition. d[18] bovf bioz fifo overfow. indicates the bioz fifo has overfowed and the data record has been corrupted. remains active until a fifo reset (recommended) or synch operation is issued. d[17] bover bioz over range. indicates the bioz output magnitude has exceeded the bioz high threshold (bloff_hi_it) for at least 100ms, recommended for use in 2 and 4 electrode bioz lead off detection. remains active as long as the condition persists, then held until cleared by status read back (32nd sclk). d[16] bundr bioz under range. indicates the bioz output magnitude has been bounded by the bioz low threshold (bloff_lo_it) for at least 1.7 seconds, recommended for use in 4 electrode bioz lead off detection. remains active as long as the condition persists, then held until cleared by status read back (32nd sclk). maxim integrated 41 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
table 12. status (0x01) register meaning (continued) index name meaning d[15] bcgmon bioz current generator monitor. indicates the drvp and/or drvn current generator has been in a lead off condition for at least 128ms, recommended for use in 4 electrode bioz lead off detection. remains active as long as the condition persists, then held until cleared by status read back (32nd sclk). d[14] pint pace fifo interrupt. indicates pace records are available for read back (should be used in conjunction with eint). remains active until all available pace fifo records have been read back. d[13] povf pace fifo overfow. indicates the pace fifo has overfowed and the data record has been corrupted. remains active until a fifo reset (recommended) or synch operation is issued. d[12] pedge pace edge detection interrupt. real time pace edge indicator showing when the MAX30001 has determined a pace edge occurred (note this is different than the pint interrupt, which indicates when the detected edges are logged into the pace fifo). clear behavior is defned by clr_ pedge[1:0], see the mngr_int (0x04) register for details. d[11] lonint ultra-low power (ulp) leads-on detection interrupt. indicates that the MAX30001 has determined it is in a leads-on condition (as selected in cnfg_gen). lonint is asserted whenever en_ulp_lon[1:0] in register cnfg_gen is set to either 01 or 10 to indicate that the ulp leads on detection mode has been enabled. the status register has to be read back once after ulp leads on detection mode has been activated to clear lonint and enable leads on detection. lonint remains active while the leads-on condition persists, then held until cleared by status read back (32nd sclk). d[10] rrint ecg r-to-r detector r event interrupt. issued when the r-to-r detector has identifed a new r event. clear behavior is defned by clr_rrint[1:0]; see mngr_int for details. d[9] samp sample synchronization pulse. issued on the ecg base-rate sampling instant, for use in assisting c monitoring and synchronizing other peripheral operations and data, generally recommended for use as a dedicated interrupt. frequency is selected by samp_it[1:0], see mngr_int for details. clear behavior is defned by clr_samp, see mngr_int for details. d[8] pllint pll unlocked interrupt. indicates that the pll has not yet achieved or has lost its phase lock. pllint will only be asserted when the pll is powered up and active (ecg and/or bioz channel enabled). remains asserted while the pll unlocked condition persists, then held until cleared by status read back (32nd sclk). d[5] bcgmp bioz current generator monitor positive output. indicates the drvp current generator has been in a lead off condition for at least 128ms. this is not strictly an interrupt bit, but is a detailed status bit, covered by the bcgmon interrupt bit. d[4] bcgmn bioz current generator monitor negative output. indicates the drvn current generator has been in a lead off condition for at least 128ms. this is not strictly an interrupt bit, but is a detailed status bit, covered by the bcgmon interrupt bit. d[3] ldoff_ph dc lead off detection detailed status. indicates that the MAX30001 has determined (as selected by cnfg_gen): ecgp is above the high threshold (v thh ), ecgp is below the low threshold (v thl ), ecgn is above the high threshold (vt hh ), ecgn is below the low threshold (v thl ), respectively. remains active as long as the leads-off detection is active and the leads-off condition persists, then held until cleared by status read back (32nd sclk). ldoff_ph to ldoff_nl are detailed status bits that are asserted at the same time as dcloffint. d[2] ldoff_pl d[1] ldoff_nh d[0] ldoff_nl maxim integrated 42 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
en_int (0x02) and en_int2 (0x03) registers en_int and en_int2 are read/write registers that govern the operation of the intb output and int2b output, respectively. the first two bytes indicate which interrupt input bits are included in the interrupt output or term (ex. a one in an en_int register indicates that the corresponding input bit is included in the intb interrupt output or term). see the status register for detailed descriptions of the interrupt bits. the power-on reset state of all en_int bits is 0 (ignored by int). en_int and en_int2 can also be used to mask persistent interrupt conditions in order to perform other interrupt-driven operations until the persistent conditions are resolved. intb_type[1:0] allows the user to select between a cmos or an open-drain nmos mode intb output. if using open- drain mode, an option for an internal 125k? pullup resistor is also offered. all intb and int2b types are active-low (intb low indicates the device requires servicing by the c); however, the open- drain mode allows the intb line to be shared with other devices in a wired-or configuration. in general, it is suggested that int2b be used to support specialized/dedicated interrupts of use in specific applications, such as the self-clearing versions of samp or rrint. table 13. en_int (0x02) and en_int2 (0x03) register maps table 14. en_int (0x02 and 0x03) register meaning reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x02 0x03 en_int en_int2 r/w en_eint en_ eovf en_ fstint en_dcl offint en_bint en_bovf en_ bover en_ bundr en_ bcgmon en_pint en_povf en_ pedge en_ lonint en_ rrint en_ samp en_ pllint x x x x x x intb_type[1:0] index name default function d[23:8] en_eint en_ eovf en_fstint en_dcloffint en_bint en_bovf en_bover en_bundr en_bcgmon en_pint en_povf en_pedge en_lonint en_ rrint en_samp en_pllint 0x0000 interrupt enables for interrupt bits in status[23:8] 0 = individual interrupt bit is not included in the interrupt or term 1 = individual interrupt bit is included in the interrupt or term d[1:0] intb_type[1:0] 11 intb port type (en_int selections) 00 = disabled (three-state) 01 = cmos driver 10 = open-drain nmos driver 11 = open-drain nmos driver with internal 125k? pullup resistance 11 int2b port type (en_int2 selections) 00 = disabled (three-state) 01 = cmos driver 10 = open-drain nmos driver 11 = open-drain nmos driver with internal 125k? pullup resistance maxim integrated 43 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
mngr_int (0x04) mngr_int is a read/write register that manages the operation of the configurable interrupt bits in response to ecg and bioz fifo conditions (see the status register and ecg and bioz fifo descriptions for more details). finally, this register contains the configuration bits supporting the sample synchronization pulse (samp) and rtor heart rate detection interrupt (rrint). table 15. mngr_int (0x04) register map table 16. mngr_int (0x04) register functionality reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x04 mngr_ int r/w efit[4:0] bfit[2:0] x x x x x x x x x clr_ fast clr_rrint[1:0] clr_ pedge clr_ samp samp_it[1:0] index name default function d[23:19] efit[4:0] 0 1111 ecg fifo interrupt threshold (issues eint based on number of unread fifo records) 00000 to 11111 = 1 to 32, respectively (i.e. efit[4:0]+1 unread records) d[18:16] bfit[2:0] 011 bioz fifo interrupt threshold (issues bint based on number of unread fifo records) 000 to 111 = 1 to 8, respectively (i.e. bfit[2:0]+1 unread records) d[6] clr_ f ast 0 fast mode interrupt clear behavior: 0 = fstint remains active until the fast mode is disengaged (manually or automatically), then held until cleared by status read back (32nd sclk). 1 = fstint remains active until cleared by status read back (32nd sclk), even if the MAX30001 remains in fast recovery mode. once cleared, fstint will not be re-asserted until fast mode is exited and re-entered, either manually or automatically. d[5:4] clr_rrint[1:0] 00 rtor r detect interrupt (rrint) clear behavior: 00 = clear rrint on status register read back 01 = clear rrint on rtor register read back 10 = self-clear rrint after one ecg data rate cycle, approximately 2ms to 8ms 11 = reserved. do not use. d[3] clr_pedge 0 pace edge detect interrupt (pedge) clear behavior 0 = clear pedge on status register read back 1 = self-clear pedge after one pace comparison cycle, roughly 16s note: self-clear mode is recommended for int2b use only. d[2] clr_samp 1 sample synchronization pulse (samp) clear behavior: 0 = clear samp on status register read back (recommended for debug/ evaluation only). 1 = self-clear samp after approximately one-fourth of one data rate cycle. d[1:0] samp_it[1:0] 00 sample synchronization pulse (samp) frequency 00 = issued every sample instant 01 = issued every 2nd sample instant 10 = issued every 4th sample instant 11 = issued every 16th sample instant maxim integrated 44 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
mngr_dyn (0x05) mngr_dyn is a read/write register that manages the settings of any general/dynamic modes within the device. the ecg fast recovery modes and thresholds are managed here. this register also contains the interrupt thresholds for bioz ac lead-off detection (see cnfg_gen for more details). unlike many cnfg registers, changes to dynamic modes do not impact fifo operations or require a synch operation (though the affected circuits may require time to settle, resulting in invalid/corrupted fifo output voltage information during the settling interval). table 17. mngr_dyn (0x05) register map table 18. mngr_dyn (0x05) register functionality reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x05 mngr_ dyn r/w fast[1:0] fast_th[5:0] bloff_hi_it[7:0] bloff_lo_it[7:0] index name default function d[23:22] fast[1:0] 00 ecg channel fast recovery mode selection (ecg high pass filter bypass): 00 = normal mode (fast recovery mode disabled) 01 = manual fast recovery mode enable (remains active until disabled) 10 = automatic fast recovery mode enable (fast recovery automatically activated when/while ecg outputs are saturated, using fast_th). 11 = reserved. do not use. d[21:16] fast_th[5:0] 0x3f automatic fast recovery threshold: if fast[1:0] = 10 and the output of an ecg measurement exceeds the symmetric thresholds defned by 2048*fast_th for more than 125ms, the fast recovery mode will be automatically engaged and remain active for 500ms. for example, the default value (fast_th = 0x3f) corresponds to an ecg output upper threshold of 0x1f800, and an ecg output lower threshold of 0x20800. d[15:8] bloff_hi_it[7:0] 0xff bioz ac lead off over-range threshold if en_bloff[1:0] = 1x and the adc output of a bioz measurement exceeds the symmetric thresholds defned by 2048*bloff_hi_it for over 128ms, the bover interrupt bit will be asserted. for example, the default value (bloff_it= 0xff) corresponds to a bioz output upper threshold of 0x7f800 or about 99.6% of the full scale range, and a bioz output lower threshold of 0x80800 or about 0.4% of the full scale range with the lsb weight 0.4%. d[7:0] bloff_lo_it[7:0] 0xff bioz ac lead off under-range threshold if en_bloff[1:0] = 1x and the output of a bioz measurement is bounded by the symmetric thresholds defned by 32*bloff_lo_it for over 128ms, the bundr interrupt bit will be asserted. maxim integrated 45 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
sw_rst (0x08) sw_rst (software reset) is a write-only register/command that resets the MAX30001 to its original default conditions at the end of the spi sw_rst transaction (i.e. the 32nd sclk rising edge). execution occurs only if din[23:0] = 0x000000. the effect of a sw_rst is identical to power-cycling the device. synch (0x09) synch (synchronize) is a write-only register/command that begins new ecg/bioz operations and recording, begin - ning on the internal mstr clock edge following the end of the spi synch transaction (i.e. the 32nd sclk rising edge). execution occurs only if din[23:0] = 0x000000. in addition to resetting and synchronizing the operations of any active ecg, rtor, bioz, and pace circuitry, synch will also reset and clear the fifo memories and the dsp filters (to mid - scale), allowing the user to effectively set the time zero for the fifo records. no configuration settings are impacted. for best results, users should wait until the pll has achieved lock before synchronizing if the cnfg_gen settings have been altered. once the device is initially powered up, it will need to be fully configured prior to launching recording operations. likewise, anytime a change to cnfg_gen, cnfg_ ecg, or cnfg_bioz registers are made there may be discontinuities in the ecg and bioz records and possibly changes to the size of the time steps recorded in the fifos. the synch command provides a means to restart operations cleanly following any such disturbances. during multi-channel operations, if a fifo overflow event occurs and a portion of the record is lost, it is recommended to use the synch command to recover and restart the recording (avoiding issues with missing data in one or more channel records). note that the two channel records cannot be directly synchronized within the device, due to significant differences in group delays, depending on filter selectionsalignment of the records will have to be done externally. fifo_rst (0x0a) fifo_rst (fifo reset) is a write-only register/command that begins a new ecg and bioz recordings by resetting the fifo memories and resuming the record with the next available ecg and bioz data. execution occurs only if din[23:0] = 0x000000. unlike the synch command, the operations of any active ecg, r-to-r, bioz, and pace circuitry are not impacted by fifo_rst, so no settling/recovery transients apply. fifo_rst can also be used to quickly recover from a fifo overflow state (recommended for single ecg or bioz channel use, see above). table 19. sw_rst (0x08) register map table 20. synch (0x09) register map table 21. fifo_rst (0x0a) register map reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x08 sw_rst r/w d[23:16] = 0x00 d[15:8] = 0x00 d[7:0] = 0x00 reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x09 synch r/w d[23:16] = 0x00 d[15:8] = 0x00 d[7:0] = 0x00 reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x0a fifo_rst r/w d[23:16] = 0x00 d[15:8] = 0x00 d[7:0] = 0x00 maxim integrated 46 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
info (0x0f) info is a read-only register that provides information about the MAX30001. the first nibble contains an alternating bit pattern to aide in interface verification. the second nibble contains the revision id. the third nibble includes part id information. note: due to internal initialization procedures, this command will not read-back valid data if it is the first com - mand executed following either a power-cycle event, or a sw_rst event. cnfg_gen (0x10) cnfg_gen is a read/write register which governs general settings, most significantly the master clock rate for all internal timing operations. anytime a change to cnfg_gen is made, there may be discontinuities in the ecg and bioz records and possibly changes to the size of the time steps recorded in the fifos. the synch command can be used to restore internal synchronization resulting from configuration changes. note when en_ecg and en_bioz are both logic-low, the device is in one of two ultra-low power modes (determined by en_ulp_lon). table 22. info (0x0f) register map table 23. info (0x0f) register meaning table 24. cnfg_gen (0x10) register map table 25. cnfg_gen (0x10) register functionality reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x0f info r 0 1 0 1 rev_id[3:0] x x 0 1 x x x x x x x x x x x x index name meaning d[19:16] rev_id[3:0] revision id reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x10 cnfg_ gen r/w en_ulp_lon[1:0] fmstr[1:0] en_ecg en_bioz en_pace x en_bloff[1:0] en_dcloff[1:0] ipol imag[2:0] vth[1:0] en_rbias[1:0] rbiasv[1:0] rbiasp rbiasn index name default function d[23:22] en_ulp_lon [1:0] 00 ultra-low power lead-on detection enable 00 = ulp lead-on detection disabled 01 = ecg ulp lead-on detection enabled 10 = reserved. do not use. 11 = reserved. do not use. ulp mode is only active when the ecg channel is powered down/disabled. maxim integrated 47 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
table 25. cnfg_gen (0x10) register functionality (continued) index name default function d[21:20] fmstr[1:0] 00 master clock frequency. selects the master clock frequency (fmstr), and timing resolution (t res ), which also determines the ecg and cal timing characteristics. these are generated from fclk, which is always 32.768khz. 00 = f mstr = 32768hz, t res = 15.26s (512hz ecg progressions) 01 = f mstr = 32000hz, t res = 15.63s (500hz ecg progressions) 10 = f mstr = 32000hz, t res = 15.63s (200hz ecg progressions) 11 = f mstr = 31968.78hz, t res = 15.64s (199.8049hz ecg progressions) d[19] en_ecg 0 ecg channel enable 0 = ecg channel disabled 1 = ecg channel enabled note: the ecg channel must be enabled to allow r-to-r operation. d[18] en_bioz 0 bioz channel enable 0 = bioz channel disabled 1 = bioz channel enabled d[17] en_pace 0 pace channel enable 0 = pace channel disabled 1 = pace channel enabled if ecg channel also enabled (en_ecg=1) d[15:14] en_bloff[1:0] 00 bioz digital lead off detection enable 00 = digital lead off detection disabled 01 = lead off under range detection, 4 electrode bioz applications 10 = lead off over range detection, 2 and 4 electrode bioz applications 11 = lead off over & under range detection, 4 electrode bioz applications ac method, requires active bioz channel , enables bover & bundr interrupt behavior. uses bioz excitation current set in cnfg_bioz with digital thresholds set in mngr_dyn. d[13:12] en_dcloff 00 dc lead-off detection enable 00 = dc lead-off detection disabled 01 = dcloff detection applied to the ecgp/n pins 10 = reserved. do not use. 11 = reserved. do not use. dc method, requires active selected channel, enables dcloff interrupt and status bit behavior. uses current sources and comparator thresholds set below. d[ 1 1] dcloff_ ipol 0 dc lead-off current polarity (if current sources are enabled/connected) 0 = ecgp - pullup ecgn C pulldown 1 = ecgp - pulldown ecgn C pullup d[10:8] imag[2:0] 000 dc lead-off current magnitude selection 000 = 0na (disable and disconnect current sources) 001 = 5na 010 = 10na 011 = 20na 100 = 50na 101 = 100na 110 = reserved. do not use. 111 = reserved. do not use. maxim integrated 48 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
table 26 shows the ecg and bioz data rates that can be realized with various setting of fmstr, along with rate configuration bits available in the cnfg_ecg and cnfg_bioz registers. note fmstr also determines the timing reso - lution of the pace detection block (and the resulting record depth with respect to the ecg_rate selection) as well as the timing resolution of the cal waveform generator. table 25. cnfg_gen (0x10) register functionality (continued) table 26. master frequency summary table index name default function d[7:6] vth[1:0] 00 dc lead-off voltage threshold selection 00 = v mid 300mv 01 = v mid 400mv 10 = v mid 450mv 11 = v mid 500mv d[5:4] en_rbias[1:0] 00 enable and select resistive lead bias mode 00 = resistive bias disabled 01 = ecg resistive bias enabled if en_ecg is also enabled 10 = bioz resistive bias enabled if en_bioz is also enabled 11 = reserved. do not use. if en_ecg or en_bioz is not asserted at the same time or prior to en_rbias[1:0] being enabled, then en_rbias[1:0] will remain set to 00. d[3:2] rbiasv[1:0] 01 resistive bias mode value selection 00 = r bias = 50m? 01 = r bias = 100m? 10 = r bias = 200m? 11 = reserved. do not use. d[1] rbiasp 0 enables resistive bias on positive input 0 = ecgp/bip is not resistively connected to v mid 1 = ecgp/bin is connected to v mid through a resistor (selected by rbiasv). d[0] rbiasn 0 enables resistive bias on negative input 0 = ecgn is not resistively connected to v mid 1 = ecgn is connected to v mid through a resistor (selected by rbiasv). fmstr [1:0] master frequency (f mstr ) (hz) ecg data rate (ecg_rate) (sps) rtor timing resolution (rtor_res) (ms) pace timing resolution (pace_res) (s) pace fifo record depth (ecg_rate) calibration timing resolution (cal_res) (s) bioz data rates (b_rate) (sps) 00 32,768 00 = 512 01 = 256 10 = 128 7.8125 15.26 00 = 128 01 = 256 1x = 512 30.52 0 = 64 1 = 32 01 32,000 00 = 500 01 = 250 10 = 125 8.000 15.63 00 = 128 01 = 256 1x = 512 31.25 0 = 62.50 1 = 31.25 10 32,000 10 = 200 8.000 15.63 320 31.25 0 = 50 1 = 25 11 31,968 10 = 199.8049 8.008 15.64 320 31.28 0 = 49.95 1 = 24.98 maxim integrated 49 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
cnfg_cal (0x12) cnfg_cal is a read/write register that configures the operation, settings, and function of the internal calibration voltage sources (vcalp and vcaln). the output of the voltage sources can be routed to the ecg or bioz/pace inputs through the channel input muxes to facilitate end-to-end testing operations. note if a vcal source is applied to a connected device, it is recommended that the appropriate channel mux switches be placed in the open position. table 27. cnfg_cal (0x12) register map table 28. cnfg_cal (0x12) register functionality reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x12 cnfg_ cal r/w x en_vcal vmode vmag x x x x x fcal[2:0] fifty thigh[10:8] thigh[7:0] index name default function d[22] en_vcal 0 calibration source (vcalp and vcaln) enable 0 = calibration sources and modes disabled 1 = calibration sources and modes enabled d[21] vmode 0 calibration source mode selection 0 = unipolar, sources swing between v mid v mag and v mid 1 = bipolar, sources swing between v mid + v mag and v mid - v mag d[20] vmag 0 calibration source magnitude selection (v mag ) 0 = 0.25mv 1 = 0.50mv d[14:12] fcal[2:0] 100 calibration source frequency selection (fcal) 000 = f mstr /128 (256, 250, or 249.75hz) 001 = f mstr /512 (64, 62.5, or 62.4375hz) 010 = f mstr /2048 (16, 15.625, or 15.609375hz) 011 = f mstr /8192 (4, 3.90625, or 3.902344hz) 100 = f mstr /2 15 (1, 0.976563, or 0.975586hz) 101 = f mstr /2 17 (0.25, 0.24414, or 0.243896hz) 110 = f mstr /2 19 (0.0625, 0.061035hz, or 0.060974hz) 111 = f mstr /2 21 (0.015625, 0.015259, or 0.015244hz) actual frequencies are determined by fmstr selection (see cnfg_gen for details), frequencies in parenthesis are based on 32,768, 32,000, or 31,968hz clocks (fmstr[1:0] = 00). tcal = 1/fcal. d[ 1 1] fifty 1 calibration source duty cycle mode selection 0 = use cal_thigh to select time high for vcalp and vcaln 1 = thigh = 50% (cal_thigh[10:0] are ignored) d[10:0] thigh[10:0] 0x000 calibration source time high selection if fifty = 1, t high = 50% (and thigh[10:0] are ignored), otherwise thigh = thigh[10:0] x cal_res cal_res is determined by fmstr selection (see cnfg_gen for details); for example, if fmstr[1:0] = 00, cal_res = 30.52s. maxim integrated 50 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
cnfg_emux (0x14) cnfg_emux is a read/write register which configures the operation, settings, and functionality of the input multiplexer associated with the ecg channel. table 29. cnfg_emux (0x14) register map table 30. cnfg_emux (0x14) register functionality figure 16. calibration voltage source options reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x14 cnfg_ emux r/w ecg_pol x ecg_ openp ecg_ openn ecg_calp_sel[1:0] ecg_caln_sel[1:0] x x x x x x x x x x x x x x x x index name default function d[23] ecg_pol 0 ecg input polarity selection 0 = non-inverted 1 = inverted d[21] ecg_openp 1 open the ecgp input switch (most often used for testing and calibration) 0 = ecgp is internally connected to the ecg afe channel 1 = ecgp is internally isolated from the ecg afe channel d[20] ecg_openn 1 open the ecgn input switch (most often used for testing and calibration) 0 = ecgn is internally connected to the ecg afe channel 1 = ecgn is internally isolated from the ecg afe channel d[19:18] ecg_calp_ sel[1:0] 00 ecgp calibration selection 00 = no calibration signal applied 01 = input is connected to v mid 10 = input is connected to vcalp (only available if cal_en_vcal = 1) 11 = input is connected to vcaln (only available if cal_en_vcal = 1) d[17:16] ecg_caln_ sel[1:0] 00 ecgn calibration selection 00 = no calibration signal applied 01 = input is connected to v mid 10 = input is connected to vcalp (only available if cal_en_vcal = 1) 11 = input is connected to vcaln (only available if cal_en_vcal = 1) calibration voltage source options v mid + 0 . 50 mv cal _ vmode = 0 cal _ vmag = 0 cal _ vmode = 1 cal _ vmag = 0 v mid v mid + 0 . 25 mv v mid - 0 . 25 mv v mid v mid + 0 . 25 mv v mid - 0 . 25 mv cal _ vmode = 0 cal _ vmag = 1 cal _ vmode = 1 cal _ vmag = 1 v mid v mid + 0 . 50 mv v mid - 0 . 50 mv v mid v mid - 0 . 50 mv t high t cal vcalp vcaln maim integrated 51 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
cnfg_ecg (0x15) cnfg_ecg is a read/write register which configures the operation, settings, and functionality of the ecg channel. anytime a change to cnfg_ecg is made, there may be discontinuities in the ecg record and possibly changes to the size of the time steps recorded in the ecg fifo. the synch command can be used to restore internal synchronization resulting from configuration changes. table 31. cnfg_ecg (0x15) register map table 32. cnfg_ecg (0x15) register functionality reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x15 cnfg_ ecg r/w ecg_rate[1:0] x x x x ecg_gain[1:0] x ecg_dhpf ecg_dlpf[1:0] x x x x x x x x x x x x index name default function d[23:22] ecg_rate[1:0] 10 ecg data rate (also dependent on fmstr selection, see cnfg_gen table 33): fmstr = 00: f mstr = 32768hz, t res = 15.26s (512hz ecg progressions) 00 = 512sps 01 = 256sps 10 = 128sps 11 = reserved. do not use. fmstr = 01: f mstr = 32000hz, t res = 15.63s (500hz ecg progressions) 00 = 500sps 01 = 250sps 10 = 125sps 11 = reserved. do not use. fmstr = 10: f mstr = 32000hz, t res = 15.63s (200hz ecg progressions) 00 = reserved. do not use. 01 = reserved. do not use. 10 = 200sps 11 = reserved. do not use. fmstr = 11: f mstr = 31968hz, t res = 15.64s (199.8hz ecg progressions) 00 = reserved. do not use. 01 = reserved. do not use. 10 = 199.8sps 11 = reserved. do not use. maxim integrated 52 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
table 33. supported ecg_rate and ecg_dlpf options table 32. cnfg_ecg (0x15) register functionality (continued) note: combinations shown in grey are unsupported and will be internally mapped to the default settings shown. cnfg_gen fmstr[1:0] ecg_rate[1:0] sample rate (sps) ecg_dlpf[1:0]/digital lpf cutoff 00 01 (hz) 10 (hz) 11 (hz) 00 = 32,768hz 00 = 512 bypass 40.96 102.4 153.6 01 = 256 bypass 40.96 102.4 40.96 10 = 128 bypass 40.96 40.96 40.96 01 = 32,000hz 00 = 500 bypass 40.00 100.0 150.0 01 = 250 bypass 40.00 100.0 40.00 10 = 125 bypass 40.00 40.00 40.00 10 = 32,000hz 10 = 200 bypass 40.00 40.00 40.00 11 = 31,968hz 10 = 199.8 bypass 39.96 39.96 39.96 index name default function d[17:16] ecg_gain[1:0] 00 ecg channel gain setting 00 = 20v/v 01 = 40v/v 10 = 80v/v 11 = 160v/v d[14] ecg_dhpf 1 ecg channel digital high-pass filter cutoff frequency 0 = bypass (dc) 1 = 0.50hz d[13:12] ecg_dlpf[1:0] 01 ecg channel digital low-pass filter cutoff frequency 00 = bypass (decimation only, no fir flter applied) 01 = approximately 40hz 10 = approximately 100hz (available for 512, 256, 500, and 250sps ecg rate selections only) 11 = approximately 150hz (available for 512 and 500sps ecg rate selections only) note: see table 33. if an unsupported dlpf setting is specifed, the 40hz setting (ecg_dlpf[1:0] = 01) will be used internally; the cnfg_ecg register will continue to hold the value as written, but return the effective internal value when read back. maxim integrated 53 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
cnfg_bmux(0x17) cnfg_bmux is a read/write register which configures the operation, settings, and functionality of the input multiplexer associated with the bioz channel. table 34. cnfg_bmux (0x17) register map table 35. cnfg_bmux (0x17) register functionality reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x17 cnfg_ bmux r/w x x bmux_openp bmux_ openn bmux_calp_sel[1:0] bmux_caln_sel[1:0] x x bmux_cg_mode[1:0] bmux_ en_bist bmux_rnom[2:0] x bmux_rmod[2:0] x x bmux_fbist[1:0] index name default function d[21] bmux_ openp 1 open the bip input switch (most often used for testing and calibration) 0 = bip is internally connected to the bioz channel 1 = bip is internally isolated from the bioz channel d[20] bmux_ openn 1 open the bin input switch (most often used for testing and calibration) 0 = bin is internally connected to the bioz channel 1 = bin is internally isolated from the bioz channel d[19:18] bmux_calp_ sel[1:0] 00 bip calibration selection (vcal application to bip/n inputs intended for use in pace testing only.) 00 = no calibration signal applied 01 = input is connected to vmid 10 = input is connected to vcalp (only available if cal_en_vcal=1) 11 = input is connected to vcaln (only available if cal_en_vcal=1) d[17:16] bmux_caln_ sel[1:0] 00 bin calibration selection (vcal application to bip/n inputs intended for use in pace testing only.) 00 = no calibration signal applied 01 = input is connected to vmid 10 = input is connected to vcalp (only available if cal_en_vcal=1) 11 = input is connected to vcaln (only available if cal_en_vcal=1) d[13:12] bmux_cg_ mode[1:0] 00 bioz current generator mode selection 00 = unchopped sources with low pass filter (higher noise, excellent 50/60hz rejection, recommended for ecg, bioz applications) 01 = chopped sources without low pass filter (low noise, no 50/60hz rejection, recommended for bioz applications with digital lpf, possibly battery powered ecg, bioz applications) 10 = chopped sources with low pass filter (low noise, excellent 50/60hz rejection) 11 = chopped sources with resistive cm setting (not recommended to be used for drive currents >32a) (low noise, excellent 50/60hz rejection, lower input impedance) maxim integrated 54 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
table 36. cnfg_bmux (0x17) rmod bist settings table 35. cnfg_bmux (0x17) register functionality (continued) bmux_rnom[2:0] bmux_rmod[2:0] nominal resistance (?) modulated resistance (m?) 000 000 001 010 1xx 5000 2960.7 980.6 247.5 unmodulated 001 000 001 010 1xx 2500 740.4 245.2 61.9 unmodulated 010 000 001 010 1xx 1667 329.1 109.0 27.5 unmodulated index name default function d[11] bmux_en_ bist 0 bioz modulated resistance built-in-self-test (rmod bist) mode enable 0 = rmod bist disabled 1 = rmod bist enabled note: available only when cnfg_cal en_vcal= 0 to avoid body interference, the bip/n switches should be open in this mode. when enabled, the drvp/n isolation switches are opened and the drvp/n-to-bip/n internal switches are engaged. also, the lead bias resistors are applied to the bioz inputs in 200m? mode. d[10:8] bmux_ rnom[2:0] 000 bioz rmod bist nominal resistance selection see rmod bist settings table for details. d[6:4] bmux_ rmod[2:0] 100 bioz rmod bist modulated resistance selection (see rmod bist settings table for details.) 000 = modulated resistance value 0 001 = modulated resistance value 1 010 = modulated resistance value 2 011 = reserved, do not use 1xx = all swmod switches open - no modulation (dc value = rnom) d[1:0] bmux_ fbist[1:0] 00 bioz rmod bist frequency selection calibration source frequency selection (fcal) 00 = f mstr /2 13 (approximately 4 hz) 01 = f mstr /2 15 (approximately 1 hz) 10 = f mstr /2 17 (approximately 1/4 hz) 11 = f mstr /2 19 (approximately 1/16 hz) actual frequencies are determined by fmstr selection (see cnfg_gen for details), approximate frequencies are based on a 32,768 hz clock (fmstr[1:0]=00). all selections use 50% duty cycle. maxim integrated 55 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
cnfg_bioz(0x18) cnfg_bioz is a read/write register which configures the operation, settings, and function of the bioz channel, including the associated modulated current generator. anytime a change to cnfg_bioz is made, there may be discontinuities in the bioz record and possibly changes to the size of the time steps recorded in the bioz fifo. the synch command can be used to restore internal synchronization resulting from configuration changes. table 36. cnfg_bmux (0x17) rmod bist settings (continued) table 37. cnfg_bioz (0x18) register map bmux_rnom[2:0] and swnom switches engaged bmux_rmod[2:0] nominal resistance (?) modulated resistance (m?) 011 000 001 1xx 1250 185.1 61.3 unmodulated 100 000 001 1xx 1000 118.5 39.2 unmodulated 101 000 001 1xx 833 82.3 27.2 unmodulated 110 000 001 1xx 714 60.5 20.0 unmodulated 111 000 001 1xx 625 46.3 15.3 unmodulated reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x18 cnfg_ bioz r/w bioz_ rate bioz_ahpf[2:0] ext_ rbias ln_bioz bioz_gain[1:0] bioz_dhpf[1:0] bioz_dlpf[1:0] bioz_fcgen[3:0] bioz_ cgmon bioz_cgmag[2:0] bioz_phoff[3:0] maxim integrated 56 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
table 38. cnfg_bioz (0x18) register functionality index name default function d[23] bioz_rate 0 bioz data rate (also dependent on fmstr selection, see cnfg_gen): fmstr = 00: f mstr = 32,768hz (512hz ecg/bioz progressions) 0 = 64sps 1 = 32sps fmstr = 01: f mstr = 32,000hz (500hz ecg/bioz progressions) 0 = 62.50sps 1 = 31.25sps fmstr = 10: f mstr = 32,000 hz (200hz ecg/bioz progressions) 0 = 50sps 1 = 25sps fmstr = 11: f mstr = 31,968 hz (199.8hz ecg/bioz progressions) 0 = 49.95sps 1 = 24.98sps d[22:20] bioz_ ahpf[2:0] 010 bioz/pace channel analog high-pass filter cutoff frequency and bypass 000 = 125hz 001 = 300hz 010 = 800hz 011 = 2000hz 100 = 3700hz 101 = 7200hz 11x = bypass ahpf d[19] ext_rbias 0 external resistor bias enable 0 = internal bias generator used 1 = external bias generator used note: use of the external resistor bias will improve the tempe rature coeffcient of all biases within the product, but the main beneft is improved cont rol of bioz current generator magnitude. if enabled, the user must include the required external resistor between rbias and gnd, and the temperature coeffcent achieved w ill be determined by the combined performance of the internal bandgap and the external resistor. d[18] ln_bioz 0 bioz channel instrumentation amplifer (ina) power mode 0 = bioz ina is in low power mode 1 = bioz ina is in low noise mode d[17:16] bioz_ gain[1:0] 00 bioz channel gain setting 00 = 10v/v 01 = 20v/v 10 = 40v/v 11 = 80v/v d[15:14] bioz_ dhpf[1:0] 00 bioz channel digital high-pass filter cutoff frequency 00 = bypass (dc) 01 = 0.05hz 1x = 0.50hz maxim integrated 57 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
table 38. cnfg_bioz (0x18) register functionality (continued) index name default function d[13:12] bioz_ dlpf[1:0] 01 bioz channel digital low-pass filter cutoff frequency 00 = bypass (decimation only, no fir flter) 01 = 4hz 10 = 8hz 11 = 16hz (available for 64, 62.5, 50, and 49.95sps bioz rate selections only) note: see table 39 below. if an unsupported dlpf setting is specifed, the 4hz setting (bioz_dlpf[1:0] = 01) will be used internally; the cnfg_bioz register will continue to hold the value as written, but return the effective internal value when read back. d[11:8] bioz_ fcgen[3:0] 1000 bioz current generator modulation frequency 0000 = 4*f mstr (approximately 128000hz) 1000 = f mstr /64 (approximately 500hz) 0001 2*f mstr (approximately 80000hz) 1001 = f mstr /128 (approximately 250hz) 0010 f mstr (approximately 40000hz) 101x = f mstr /256 (approximately 125hz) 0011 f mstr /2 (approximately 18000hz) 11xx = f mstr /256 (approximately 125hz) 0100 = f mstr /4 (approximately 8000hz) 0101 = f mstr /8 (approximately 4000hz) 0110 = f mstr /16 (approximately 2000hz) 0111 = f mstr /32 (approximately 1000hz) actual frequencies determined by fmstr selection, see cnfg_gen register and table below for details. frequencies expected between approximately16khz and approximately 64khz are offset to approximately18khz to approximately 80khz to reduce ecg/pace channel crosstalk. pace operation is only supported at approximately 40khz and approximately 80khz offset selections: fcgen[3:0] = 0001,0010, at other selections, pace will be rendered inoperable. d[7] bioz_ cgmon 0 bioz current generator monitor 0 = current generator monitors disabled 1 = current generator monitors enabled, requires active bioz channel and current generators. enables bcgmon interrupt and status bit behavior. monitors current source compliance levels, useful in detecting drvp/drvn lead off conditions with 4 electrode bioz applications. d[6:4] bioz_ cgmag[2:0] 000 bioz current generator magnitude 000 = off (drvp and drvn foating, current generators off) 001 = 8a 010 = 16a 011 = 32a 100 = 48a 101 = 64a 110 = 80a 111 = 96a see table 40 and 41 below for a list of allowed bioz_cgmag settings vs. fcgen selections. d[3:0] bioz_ phoff[3:0] 0000 bioz current generator modulation phase offset phase resolution and offset depends on bioz_fcgen setting: bioz_fcgen[3:0] 0010: phase offset = bioz_phoff[3:0]*11.25 (0 to 168.75) bioz_fcgen[3:0] = 0001: phase offset = bioz_phoff[3:1]*22.50 (0 to 157.50) bioz_fcgen[3:0] = 0000: phase offset = bioz_phoff[3:2]*45.00 (0 to 135.00) maxim integrated 58 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
table 39. supported bioz_rate and bioz_dlpf options table 40. actual bioz current generator modulator frequencies vs. fmstr[1:0] selection note: combinations shown in grey are unsupported and will be internally mapped to the default settings shown. note: shaded selections are intentionally offset to improve ecg/pace system crosstalk. cnfg_gen fmstr[1:0] bioz_rate sample rate bioz_dlpf[1:0] / digital lpf cut off 00 01 10 11 00 = 32,768hz 0 = 64sps bypass 4.096hz 8.192hz 16.384hz 1 = 32sps 4.096hz 01 = 32,000hz 0 = 62.5sps bypass 4.0hz 8.0hz 16.0hz 1 = 31.25sps 4.0hz 10 = 32,000hz 0 = 50sps bypass 4.0hz 8.0hz 16.0hz 1 = 25sps 4.0hz 11 = 31,968hz 0 = 49.95sps bypass 3.996hz 7.992hz 15.984hz 1 = 25.98sps 3.996hz bioz_fcgen[3:0] bioz current generator modulation frequency (hz) fmstr[1:0] = 00 f mstr = 32,768hz fmstr[1:0] = 01 f mstr = 32,000hz fmstr[1:0] = 10 f mstr = 32,000hz fmstr[1:0] = 11 f mstr = 31,968hz 0000 131,072 128,000 128,000 127,872 0001 81,920 80,000 80,000 81,920 0010 40,960 40,000 40,000 40,960 0011 18,204 17,780 17,780 18,204 0100 8,192 8,000 8,000 7,992 0101 4,096 4,000 4,000 3,996 0110 2,048 2,000 2,000 1,998 0111 1,024 1,000 1,000 999 1000 512 500 500 500 1001 256 250 250 250 101x, 11xx 128 125 125 125 maxim integrated 59 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
cnfg_pace (0x1a) register cnfg_pace is a read/write register which configures the operation, settings, and function of the pace detection channel. portions of the pace afe are shared with the bioz channel so anytime a change to cnfg_bioz or cnfg_pace is made, there may be discontinuities in the combined ecg/pace fifo output. the synch command can be used to restore internal synchronization resulting from configuration changes. note if enabling the pace function, the analog high-pass filter in the shared bioz/pace afe must be set to the desired value via bioz_ahpf[1:0] in the cnfg_bioz register, even if the bioz function is disabled (en_bioz = 0 in cnfg_gen register. table 41. allowed cgmag option vs. fcgen selections table 42. cnfg_pace (0x1a) register map reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x1a cnfg_ pace r/w pace_ pol x x x diff_off pace_gain[2:0] x aout_lbw aout[1:0] x x x x pace_dacp[3:0] pace_dacn[3:0] fcgen[3:0] approximate current generator modulation frequency (hz) cgmag[2:0] options allowed current generator magnitude options allowed (a pp ) 0000 12,8000 all all 0001 80,000 0010 40,000 0011 18,000 0100 8,000 all except 111 all except 96 0101 4,000 000, 001, 010, 011 off, 8, 16, 32 0110 2,000 000, 001, 010 off, 8, 16 0111 1,000 000, 001 off, 8 1000 500 1001 250 101x, 11xx 125 maxim integrated 60 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
table 43. cnfg_pace (0x1a) register functionality index name default function d[23] pace_pol 0 pace input polarity selection 0 = non-inverted 1 = inverted d[19] diff_off 0 pace differentiator (derivative) mode 0 = enable differentiator function (default) 1 = disable differentiator function, using sample and hold function d[18:16] pace_ gain[2:0] 000 pace channel gain selection normal mode ina out mode pga out mode (aout = 00) (aout = 01) (aout = 10) 000 = 45*4*3 = 540 45*1.125 = 50.625 45*4*1.125 = 202.50 001 = 45*2*3 = 270 45*1.125 = 50.625 45*2*1.125 = 101.25 010 = 20*4*3 = 240 20*1.125 = 22.500 20*4*1.125 = 90.00 011 = 20*2*3 = 120 20*1.125 = 22.500 20*2*1.125 = 45.00 100 = 5*4*3 = 60 5*1.125 = 5.625 5*4*1.125 = 22.50 101 = 5*2*3 = 30 5*1.125 = 5.625 5*2*1.125 = 11.25 110 = 2.2*4*3 = 26.4 5*1.125 = 5.625 5*4*1.125 = 22.50 111 = 2.2*2*3 = 13.2 5*1.125 = 5.625 5*2*1.125 = 11.25 d[14] aout_lbw 0 pace analog output buffer bandwidth mode 0 = maximum bw (approximately 100khz) 1 = limited bw (approximately 16khz) this selection is only relevant when the aout buffer is active aout 00. d[13:12] aout[1:0] 00 pace single ended analog output buffer signal monitoring selection 00 = analog output buffer disabled 01 = pace ina output 10 = pace pga output 11 = pace input to comparators d[7:4] pace_ dacp[3:0] 0101 pace detector positive comparator threshold vdacp = pace_dacp[3:0]*22.5mv (+112.5mv default) d[3:0] pace_ dacn[3:0] 0101 pace detector negative comparator threshold vdacn = -pace_dacn[3:0]*22.5mv (-112.5mv default) maxim integrated 61 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
cnfg_rtor1 and cnfg_rtor2 (0x1d and 0x1e) cnfg_rtor is a two-part read/write register that configures the operation, settings, and function of the r-to-r heart rate detection block. the first register contains algorithmic voltage gain and threshold parameters, the second contains algorithmic timing parameters. table 44. cnfg_rtor1 and cnfg_rtor2 (0x1d and 0x1e) register maps table 45. cnfg_rtor1 (0x1d) register functionality reg name r/w 23/15/7 22/14/6 21/13/5 20/12/4 19/11/3 18/10/2 17/9/1 16/8/0 0x1d cnfg_ rtor1 r/w wndw[3:0] rgain[3:0] en_ rtor x pavg[1:0] ptsf[3:0] x x x x x x x x 0x1e cnfg_ rtor2 r/w x x hoff[5:0] x x ravg[1:0] x rhsf[2:0] x x x x x x x x index name default function cnfg_rtor1 (0x1d) d[23:20] wndw[3:0] 00 1 1 this is the width of the averaging window, which adjusts the algorithm sensitivity to the width of the qrs complex. r-to-r window averaging (window width = wndw[3:0]*8ms) 0000 = 6 x rtor_res 0001 = 8 x rtor_res 0010 = 10 x rtor_res 0011 = 12 x rtor_res (default = 96ms) 0100 = 14 x rtor_res 0101 = 16 x rtor_res 0110 = 18 x rtor_res 0111 = 20 x rtor_res 1000 = 22 x rtor_res 1001 = 24 x rtor_res 1010 = 26 x rtor_res 1011 = 28 x rtor_res 1100 = reserved. do not use. 1101 = reserved. do not use. 1110 = reserved. do not use. 1111 = reserved. do not use. the value of rtor_res is approximately 8ms, see table 26. d[19:16] rgain[3:0] 1111 r-to-r gain (where gain = 2^rgain[3:0], plus an auto-scale option). this is used to maximize the dynamic range of the algorithm. 0000 = 1 1000 = 256 0001 = 2 1001 = 512 0010 = 4 1010 = 1024 0011 = 8 1011 = 2048 0100 = 16 1100 = 4096 0101 = 32 1101 = 8192 0110 = 64 1110 = 16384 0111 = 128 1111 = auto-scale (default) in auto-scale mode, the initial gain is set to 64. maxim integrated 62 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
table 45. cnfg_rtor1 (0x1d) register functionality (continued) table 46. cnfg_rtor2 (0x1e) register functionality index name default function d[15] en_rtor 0 ecg r-to-r detection enable 0 = r-to-r detection disabled 1 = r-to-r detection enabled if en_ecg is also enabled. d[13:12] pavg[1:0] 10 r-to-r peak averaging weight factor this is the weighting factor for the current r-to-r peak observation vs. past peak observations when determining peak thresholds. lower numbers weight current peaks more heavily. 00 = 2 01 = 4 10 = 8 (default) 11 = 16 peak_average(n) = [peak(n) + (pavg-1) x peak_average(n-1)] / pavg. d[11:8] ptsf[3:0] 0011 r-to-r peak threshold scaling factor this is the fraction of the peak average value used in the threshold computation. values of 1/16 to 16/16 are selected by (ptsf[3:0]+1)/16, default is 4/16. cnfg_rtor2 (0x1e) d [21:16] hoff[5:0] 10_0000 r-to-r minimum hold off this sets the absolute minimum interval used for the static portion of the hold off criteria. values of 0 to 63 are supported, default is 32 t hold_off_min = hoff[5:0] * t rtor , where t rtor is approximately 8ms, as determined by fmstr[1:0] in the cnfg_gen register. (representing approximately ? second). the r-to-r hold off qualifcation interval is t hold_off = max(t hold_off_min , t hold_off_dyn ) (see below). d[13:12] ravg[1:0] 10 r-to-r interval averaging weight factor this is the weighting factor for the current r-to-r interval observation vs. the past interval observations when determining dynamic holdoff criteria. lower numbers weight current intervals more heavily. 00 = 2 01 = 4 10 = 8 (default) 11 = 16 interval_average(n) = [interval(n) + (ravg-1) x interval_average(n-1)] / ravg. d[10:8] rhsf[2:0] 100 r-to-r interval hold off scaling factor this is the fraction of the r-to-r average interval used for the dynamic portion of the holdoff criteria (t hold_offdyn ). values of 0/8 to 7/8 are selected by rtor_rhsf[3:0]/8, default is 4/8. if 000 (0/8) is selected, then no dynamic factor is used and the holdoff criteria is determined by hoff[5:0] only (see above). maxim integrated 63 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
fifo memory description the device provides read only fifo memory for ecg, bioz, and pace information. a single memory register is also supported for heart rate detection output data (r-to-r). the operation of these fifo memories and reg - isters is detailed in the following sections. table 47 summarizes the method of access and data structure within the fifo memory. ecg fifo memory (32 words x 24 bits) the ecg fifo memory is a standard circular fifo con - sisting of 32 words, each with 24 bits of information. the ecg fifo is independently managed by internal read and write pointers. the read pointer is updated in response to the 32nd sclk rising edge in a normal mode read back transaction and on the (32 + n x 24)th sclk rising edge(s) in a burst mode transaction where n = 0 to up to 31. once a fifo sample is marked as read, it can - not be accessed again. the write pointer is governed internally. to aide data management and reduce c overhead, the device pro - vides a user-programmable ecg fifo interrupt threshold (efit[4:0]) governing the ecg interrupt bit (eint). this threshold can be programmed with values from 1 to 32, rep - resenting the number of unread ecg fifo entries required before the eint bit will be asserted, alerting the c that there is a significant amount of data in the ecg fifo ready for read back (see mngr_int (0x04) for details). do not read beyond the last valid fifo word to prevent possible data corruption. if the write pointer ever traverses the entire fifo array and catches up to the read pointer (due to failure of the c to read/maintain fifo data), a fifo overflow will occur and data will be corrupted. the eovf status and tag bits will indicate this condition and the fifo should be cleared before continuing measurements using either a synch or fifo_rst commandnote overflow events will result in the loss of samples and thus timing information, so these conditions should not occur in well- designed applications. table 47. fifo memory access and data structure summary reg fifo and mode data structure (d[23:0]) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x20 ecg burst ecg sample voltage data [17:0] etag [2:0] ptag [2:0] 0x21 ecg ecg sample voltage data [17:0] etag [2:0] ptag [2:0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x22 bioz burst bioz sample voltage data [19:0] 0 btag [2:0] 0x23 bioz bioz sample voltage data [19:0] 0 btag [2:0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x25 rtor rtor interval timing data [13:0] 0 0 0 0 0 0 0 0 0 0 maxim integrated 64 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
ecg fifo data structure the data portion of the word contains the 18-bit ecg volt - age information measured at the requested sample rate in left justified twos complement format. the remaining six bits of data hold important data tagging information (see details in table 48 and table 49 ). ecg data tags (etag) three bits in the sample record are used as an ecg data tag (etag[2:0] = d[5:3]). this section outlines the meaning of the various data tags used in the ecg fifo and recommended handling within the continuous ecg record. valid: etag = 000 indicates that ecg data for this sample represents both a valid voltage and time step in the ecg record. fast: etag = 001 indicates that ecg data for this sample was taken in the fast settling mode and that the voltage information in the sample should be treated as transient and invalid. note that while the voltage data is invalid, samples of this type do represent valid time steps in the ecg record. valid eof: etag = 010 indicates that ecg data for this sample represents both a valid voltage and time step in the ecg record, and that this is the last sample currently available in the ecg fifo (end-of-file, eof). the c should wait until further samples are available before requesting more data from the ecg fifo. fast eof: etag = 011 indicates that ecg data for this sample was taken in the fast settling mode and that the voltage information in the sample should be treated as transient and invalid. note that while the voltage data is invalid, samples of this type do represent valid time steps table 48. ecg fifo - ecg data tags (etag[2:0] = d[5:3]) etag [2:0] meaning detailed description recommended user action data valid time valid 000 v alid sample this is a valid fifo sample. log sample into ecg record and increment the time step. continue to gather data from the ecg fifo. y es y es 001 fast mode sample this sample was taken while the ecg channel was in a fast recovery mode. the voltage information is not valid, but the sample represents a valid time step. discard, note, or post-process this voltage sample, but increment the time base. continue to gather data from the ecg fifo. no y es 010 last v alid sample (eof) this is a valid fifo sample, but this is the last sample currently available in the fifo (end of file indicator). log sample into ecg record and increment the time step. suspend read back operations on the ecg fifo until more samples are available. y es y es 0 11 last fast mode sample (eof) see above (etag=001), but in addition, this is the last sample currently available in the fifo (end of file indicator). discard, note, or post-process this voltage sample, but increment the time base. suspend read back operations on the ecg fifo until more samples are available. no y es 10x unused -- -- 1 10 fifo empty (exception) this is an invalid sample provided in response to an spi request to read an empty fifo. discard this sample, without incrementing the time base. suspend read back operations on this fifo until more samples are available. no no 111 fifo overfow (exception) the fifo has been allowed to overfow C the data is corrupted. issue a fifo_rst command to clear the fifos or re-synch if necessary. note the corresponding halt and resumption in ecg/bioz time/voltage records. no no maxim integrated 65 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
in the ecg record. in addition, this is the last sample cur - rently available in the ecg fifo (end-of-file, eof). the c should wait until further samples are available before requesting more data from the ecg fifo. empty: etag = 110 is appended to any requested read back data from an empty ecg fifo. the presence of this tag alerts the user that this fifo data does not represent a valid sample or time step. note that if handled properly by the c, an occurrence of an empty tag will not com - promise the integrity of a continuous ecg record C this tag only indicates that the read back request was either premature or unnecessary. overflow: etag = 111 indicates that the ecg fifo has overflowed and that there are interruptions or missing data in the sample records. the ecg overflow (eovf) bit is also included in the status register. a fifo_reset is required to resolve this situation, effectively clearing the fifo so that valid sampling going forward is assured. depending on the application, it may also be necessary to resynchronize the MAX30001 internal channel opera - tions to move forward with valid recordings, the synch command can perform this function while also resetting the fifo memories. ecg pace data tag (ptag) the pace fifo data content is closely linked to ecg fifo content. if an ecg fifo samples has related pace information, this is indicated by a three bit pace tag (ptag[2:0] = d[2:0]) appended to and read back at the end of the ecg fifo sample. a pace tag (ptag) value between 000 and 101 (inclu - sive) indicates that a pace event was detected during the sample interval associated with and following the tagged ecg sample. in these cases, ptag stores a pointer to the appropriate location within the pace fifo where the relevant pace information is stored (see pace fifo memory for more details). a ptag value of 111 indicates no pace events were associated with the ecg sample. table 49. ecg fifo - pace data tags (ptag[2:0] = d[2:0]) ptag [2:0] detailed description pace group recommended user action 000 pace event detected 0 associate pace group 0 data with this ecg data sample. follow etag recommended user actions. 001 pace event detected 1 associate pace group 1 data with this ecg data sample. follow etag recommended user actions. 010 pace event detected 2 associate pace group 2 data with this ecg data sample. follow etag recommended user actions. 011 pace event detected 3 associate pace group 3 data with this ecg data sample. follow etag recommended user actions. 100 pace event detected 4 associate pace group 4 data with this ecg data sample. follow etag recommended user actions. 101 pace event detected 5 associate pace group 5 data with this ecg data sample. follow etag recommended user actions. 110 unused - - 111 no pace detected - associate pace group 0 with this ecg data sample. follow etag recommended user actions. maxim integrated 66 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
bioz fifo memory (8 words x 24 bits) the bioz fifo memory is a standard circular fifo consisting of 8 words, each with 24 bits of information. the bioz fifo is independently managed by internal read and write pointers. the read pointer is updated in response to the 32nd sclk rising edge in a normal mode read back transaction and on the (32 + n x 24)th sclk rising edge(s) in a burst mode transaction where n = 0 to up to 31. once a fifo sample is marked as read, it can - not be accessed again. the write pointer is governed internally. to aide data management and reduce c overhead, the device pro - vides a user-programmable bioz fifo interrupt threshold (bfit[2:0]) governing the bioz interrupt bit (bint). this threshold can be programmed with values from 1 to 8, rep - resenting the number of unread bioz fifo entries required before the bint bit will be asserted, alerting the c that there is a significant amount of data in the bioz fifo ready for read back (see mngr_int (0x04) for details). if the write pointer ever traverses the entire fifo array and catches up to the read pointer (due to failure of the c to read/maintain fifo data), a fifo overflow will occur and data will be corrupted. the bovf status and tag bits will indicate this condition and the fifo should be cleared before continuing measurements using either a synch or fifo_rst commandnote overflow events will result in the loss of samples and thus timing information, so these conditions should not occur in well- designed applications. do not read beyond the last valid fifo word to prevent possible data corruption. bioz fifo data structure the data portion of the word contains the 20-bit bioz volt - age information measured at the requested sample rate in left justified twos complement format. one bit is set to 0 and the remaining three bits of data hold important data tagging information (see details in table 50 ). table 50. bioz fifo bioz data tags (btag[2:0] = d[2:0]) btag [2:0] description recommended user action data valid time valid 000 valid sample log sample into bioz record and increment the time step. continue to read data from the bioz fifo. yes yes 001 over/under range sample log sample into bioz record and increment the time step. determine if the data is valid or a lead off condition. continue to read data from the bioz fifo. ? yes 010 last valid sample (eof) log sample into bioz record and increment the time step. suspend read of the bioz fifo until more samples are available. yes yes 0 11 last over/under range sample (eof) log sample into bioz record and increment the time step. determine if the data is valid or a lead off condition. suspend read of the bioz fifo until more samples are available. ? yes 10x unused - - - 1 10 fifo empty (exception) discard this sample without incrementing the time base. suspend read of the bioz fifo until more samples are available. no no 111 fifo overfow (exception) discard this sample without incrementing the time base. issue a fifo_rst command to clear the fifos or re-synch if necessary. note the corresponding halt and resumption in all the fifos. no no maxim integrated 67 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
bioz data tags (btag) the final three bits in the sample are used as a data tag (btag[2:0] = d[2:0]) to assist in managing data transfers. the btag structure used is detailed below. valid: btag = 000 indicates that bioz data for this sample represents both a valid voltage and time step in the bioz record. over or under range: btag = 001 indicates that bioz data for this sample violated selected range thresh - olds (see mngr_dyn and cnfg_gen) and that the voltage information in the sample should be evaluated to see if it is valid or indicative of a leads-off condition. note that while the voltage data may be invalid, samples of this type do represent valid time steps in the bioz record. valid eof: btag = 010 indicates that bioz data for this sample represents both a valid voltage and time step in the bioz record, and that this is the last sample currently available in the bioz fifo (end-of-file, eof). the c should wait until further samples are available before requesting more data from the bioz fifo. over or under range eof: btag = 011 indicates that bioz data for this sample violated selected range thresholds (see mngr_dyn and cnfg_gen) and that the voltage information in the sample should be evaluated to see if it is valid or indicates a leads-off condition. note that while the voltage data may be invalid, samples of this type do represent valid time steps in the bioz record. this is also the last sample currently available in the bioz fifo (end-of-file, eof). the c should wait until further samples are available before requesting more data from the bioz fifo. empty: btag = 110 is appended to any requested read back data from an empty bioz fifo. the presence of this tag alerts the user that this fifo data does not represent a valid sample or time step. note that if handled properly by the c, an occurrence of an empty tag will not com - promise the integrity of a continuous bioz record C this tag only indicates that the read back request was either premature or unnecessary. overflow: btag = 111 indicates that the bioz fifo has overflowed and that there are interruptions or missing data in the sample records. the bioz overflow (bovf) bit is also included in the status register. a fifo_reset is required to resolve this situation, effectively clearing the fifo so that valid sampling going forward is assured. depending on the application, it may also be necessary to resynchronize the MAX30001 internal channel operations to move forward with valid recordings, the synch command can perform this function while also resetting the fifo memories. r-to-r interval memory register (1 word x 24 bits) the r-to-r interval (rtor) memory register is a single read-only register consisting of 14 bits of timing interval information, left justified (and 10 unused bits, set to zero). the rtor register stores the time interval between the last two r events, as identified by the r-to-r detection circuitry, which operates on the ecg output data. each lsb in the rtor register is approximately equal to 8ms (cnfg_gen for exact figures). the resulting 14-bit stor - age interval can thus be approximately 130 seconds in length, again depending on device settings. each time the r-to-r detector identifies a new r event, the rtor register is updated, and the rrint interrupt bit is asserted (see status register for details). users wishing to log heart rate based on rtor register data should set clr_rrint equals 01 in the mngr_int register. this will clear the rrint interrupt bit after the rtor register has been read back, preparing the device for identification of the next r-to-r interval. users wishing to log heart rate based on the time elapsed between rrint assertions using the c to keep track of the time base (and ignoring the rtor register data) have two choices for interrupt management. if clr_rrint equals 00 in the mngr_int register, the rrint inter - rupt bit will clear after each status register read back, preparing the device for identification of the next r-to-r interval. if clr_rrint equals 10 in the mngr_int reg - ister, the rrint interrupt bit will self-clear after each one full ecg data cycle has passed, preparing the device for identification of the next r-to-r interval (this mode is rec - ommended only if using the int2b as a dedicated heart rate indicator). if clr_rrint = 0x (interrupt mode) and the r-to-r detec - tor reaches an overflow state after several minutes without detection of an r event, it will assert the rrint term with a rtor register value = 0x3fff, indicating the overflow condition. this interrupt creates a time stamp, allowing the c to keep track of the time interval between detected r events, even if the signal is lost for a prolonged amount of time. this is important if the rtor register data is the sole source to keep track of the time base. in the event of an overflow, the rtor register will be reset after being read back, allowing the c to track multiple subsequent overflow conditions. rrint is reset independently of the rtor register by an appropriate read back operation as specified by the setting of clr_rrint. maxim integrated 68 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
if clr_rrint = 1x (indicator mode) and the r-to-r detector reaches an overflow state after several minutes without detection of an r event, the counter will simply roll over, and the lack of the rrint activity on the dedicated int2b line will inform the c that no r-to-r activity was detected. generating an interrupt to keep track of the absolute time is not required in this case, as this mode will be used in a system where the c is used to keep track of the time base. pace0 to pace5 (0x30 to 0x47) register groups the pace0 to pace5 register groups are six read only memories used to store pace edge information detected by the pacemaker detection circuitry. each pace regis - ter group stores data for up to six pace edges detected between two consecutive ecg data samples stored in the ecg_fifo register and are associated with the leading ecg data sample. the ptag[2:0] bits for the associated ecg data sample indicate if one or more pace edges were detected and which pace group it was written to. each pace register group is organized into three sub- group registers denoted by an a, b, or c suffix that are divided into two segments each holding pace edge data for a total of 6 pace edges per group and a grand total of 36 pace edges in 18 registers. table 51. pace0 to pace5 (0x30 to 0x47) register map reg name r/w 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x30 pace0_burst r burst read of pace0_a, pace0_b & pace0_c registers (80-bit frame: 8-bit command + 3*24-bit data) 0x31 pace0_a r pace0_0data[9:0] p0_0rfb p0_0lst pace0_1data[9:0] p0_1rfb p0_1lst 0x32 pace0_b r pace0_2data[9:0] p0_2rfb p0_2lst pace0_3data[9:0] p0_3rfb p0_3lst 0x33 pace0_c r pace0_4data[9:0] p0_4rfb p0_4lst pace0_5data[9:0] p0_5rfb p0_5lst 0x34 pace1_burst r burst read of pace1_a, pace1_b & pace1_c registers (80-bit frame: 8-bit command + 3*24-bit data) 0x35 pace1_a r pace1_0data[9:0] p1_0rfb p1_0lst pace1_1data[9:0] p1_1rfb p1_1lst 0x36 pace1_b r pace1_2data[9:0] p1_2rfb p1_2lst pace1_3data[9:0] p1_3rfb p1_3lst 0x37 pace1_c r pace1_4data[9:0] p1_4rfb p1_4lst pace1_5data[9:0] p1_5rfb p1_5lst 0x38 pace2_burst r burst read of pace2_a, pace2_b & pace2_c registers (80-bit frame: 8-bit command + 3*24-bit data) 0x39 pace2_a r pace2_0data[9:0] p2_0rfb p2_0lst pace2_1data[9:0] p2_1rfb p2_1lst 0x3a pace2_b r pace2_2data[9:0] p2_2rfb p2_2lst pace2_3data[9:0] p2_3rfb p2_3lst 0x3b pace2_c r pace2_4data[9:0] p2_4rfb p2_4lst pace2_5data[9:0] p2_5rfb p2_5lst 0x3c pace3_burst r burst read of pace3_a, pace3_b & pace3_c registers (80-bit frame: 8-bit command + 3*24-bit data) 0x3d pace3_a r pace3_0data[9:0] p3_0rfb p3_0lst pace3_1data[9:0] p3_1rfb p3_1lst 0x3e pace3_b r pace3_2data[9:0] p3_2rfb p3_2lst pace3_3data[9:0] p3_3rfb p3_3lst 0x3f pace3_c r pace3_4data[9:0] p3_4rfb p3_4lst pace3_5data[9:0] p3_5rfb p3_5lst 0x40 pace4_burst r burst read of pace4_a, pace4_b & pace4_c registers (80-bit frame: 8-bit command + 3*24-bit data) 0x41 pace4_a r pace4_0data[9:0] p4_0rfb p4_0lst pace4_1data[9:0] p4_1rfb p4_1lst 0x42 pace4_b r pace4_2data[9:0] p4_2rfb p4_2lst pace4_3data[9:0] p4_3rfb p4_3lst 0x43 pace4_c r pace4_4data[9:0] p4_4rfb p4_4lst pace4_5data[9:0] p4_5rfb p4_5lst 0x44 pace5_burst r burst read of pace5_a, pace5_b & pace5_c registers (80-bit frame: 8-bit command + 3*24-bit data) 0x45 pace5_a r pace5_0data[9:0] p5_0rfb p5_0lst pace5_1data[9:0] p5_1rfb p5_1lst 0x46 pace5_b r pace5_2data[9:0] p5_2rfb p5_2lst pace5_3data[9:0] p5_3rfb p5_3lst 0x47 pace5_c r pace5_4data[9:0] p5_4rfb p5_4lst pace5_5data[9:0] p5_5rfb p5_5lst maxim integrated 69 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
the pace register groups are written sequentially in time as groups of pace edges are found between ecg data samples starting with pace0 and written in a circular fashion such that after pace5 is written then pace0 will be the next group written. within each pace group, the data for each pace edge is also written sequentially in time by segment starting with edge 0 but is not writ - ten in a circular fashion such that only the first six pace edges between ecg data samples is written to each pace group. if there are more than six edges in a pace group then this data will not be stored and will be lost. a sub- group register written with data for either one or two pace edges is marked as unread and if just the first segment is written then the second segment will be set to 0xfff. a sub-group register not written with any pace edge data will be set to 0xfff fff and marked as read. all unread subgroups need to be read in order for the pace group to be marked as read. a register is marked as read on the 32nd sclk rising edge in a normal (single word) mode read. there are burst mode registers for each pace regis - ter group in order to read all three sub-groups (a, b, and c) during the same serial data transfer. during the burst mode, the sub-groups are marked as read on the 32nd, 56th, and 80th sclk rising edges for sub-groups a, b, and c, respectively. burst mode cycles beyond the 80th sclk edge will not continue read back with the next pace register group; instead the data returned will read 0xfff. whenever a set of pace edges are detected between ecg data samples, the pace interrupt bit (pint) is assert - ed, alerting the c that there is new pace data ready for read back. the c should first read back the ecg fifo data to the point where the ptagd samples are identi - fied, and then read back the linked pace register group, ensuring the pace events are associated with the correct ecg data samples. examples are provided below. if new pace edge information is written to a previously written and unread pace register group then the pace overflow status bit, povr will be asserted and the association with the ecg data sample will be corrupted. in the event that the data is corrupted then either a synch or fifo_rst command should be executed to restore synchronization between the ecg data samples and the pace register groups. table 52. pace0 to pace5 (0x30 to 0x47) register functionality index name default function d[23:14], d[11:2] pacex_ydata[9:0] 0x3ff pace edge timing data pace edge timing = pacex_ydata[9:0]*t res where t res = 1/(2*f mstr ) and is set by the fmstr[1:0] bits in the cnfg_gen register. the time is relative to the associated ecg data sample. x = 0 to 5 and is the pace group associated with a specifc ecg data output sample. y = 0 to 5 and is the numbered order of the pace edges detected in time. d[13], d[1] px_yrfb 1 pace edge polarity 0 = falling edge 1 = rising edge x = 0 to 5 and is the pace group associated with a specifc ecg data output sample. y = 0 to 5 and is the numbered order of the pace edges detected in time. d[12], d[0] px_ylst 1 last pace edge 0 = additional pace edges detected in the group 1 = last pace edge detected in the group or an empty record. x = 0 to 5 and is the pace group associated with a specifc ecg data output sample. y = 0 to 5 and is the numbered order of the pace edges detected in time. maxim integrated 70 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
ecg and pace data management examples and use cases the figures and examples below illustrate several valid means of managing an example set of ecg fifo and pace register group data. data for use in the examples is given in the tables below. table 53 shows the internal state of the ecg fifo for pur - poses of these examples. the example assumes informa - tion in locations 0-7 were previously read back (indicated by y in the read column) and that data in locations 16 and beyond was either previously read back or empty (indicated by in the read column). table 53. ecg fifo example read index ecg fifo data d[23:0] ecg_data[17:0] etag[2:0] ptag[2:0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 y 0 ecg sample 00 voltage data [17:0] = 0x000 - - 1 1 1 1 y 1 ecg sample 01 voltage data [17:0] = 0x001 - - 1 1 1 1 y 2 ecg sample 02 voltage data [17:0] = 0x002 - 0 0 1 1 1 y 3 ecg sample 03 voltage data [17:0] = 0x003 - 0 0 1 1 1 y 4 ecg sample 04 voltage data [17:0] = 0x004 - 0 0 1 1 1 y 5 ecg sample 05 voltage data [17:0] = 0x005 - 0 0 0 0 0 y 6 ecg sample 06 voltage data [17:0] = 0x006 - 0 0 1 1 1 y 7 ecg sample 07 voltage data [17:0] = 0x007 - 0 0 1 1 1 8 ecg sample 08 voltage data [17:0] = 0x008 - 0 0 1 1 1 9 ecg sample 09 voltage data [17:0] = 0x009 - 0 0 1 1 1 10 ecg sample 10 voltage data [17:0] = 0x00a - 0 0 0 0 1 11 ecg sample 11 voltage data [17:0] = 0x00b - 0 0 0 1 0 12 ecg sample 12 voltage data [17:0] = 0x00c - 0 0 1 1 1 13 ecg sample 13 voltage data [17:0] = 0x00d - 0 0 1 1 1 14 ecg sample 14 voltage data [17:0] = 0x00e - 0 0 1 1 1 15 ecg sample 15 voltage data [17:0] = 0x00f - 0 0 1 1 1 16 empty 17 empty maxim integrated 71 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
table 54 shows the internal state of the first four groups in the pace register group for purposes of these examples. the example assumes information in group 0 was previ - ously read back (indicated by y in the read column), that unused words in active groups 1 and 2 were internally marked as read (indicated by in the read column), and that the empty groups 3, 4, and 5 are also internally marked as read and filled with default data. table 54. pace fifo example read index pace data d[23:0] edge timing data segment [9:0] rfb lst edge timing data segment [9:0] rfb lst 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 y 0a group 0: edge 0 timing data [9:0] = 0x000 1 0 group 0: edge 1 timing data [9:0] = 0x011 0 0 y 0b group 0: edge 2 timing data [9:0] = 0x022 1 0 group 0: edge 3 timing data [9:0] = 0x033 0 1 y 0c group 0: edge 4 timing data [9:0] = 0x3ff 1 1 group 0: edge 5 timing data [9:0] = 0x3ff 1 1 1a group 1: edge 0 timing data [9:0] = 0x100 1 0 group 1: edge 1 timing data [9:0] = 0x108 0 0 1b group 1: edge 2 timing data [9:0] = 0x110 1 1 group 1: edge 3 timing data [9:0] = 0x3ff 1 1 1c group 1: edge 4 timing data [9:0] = 0x3ff 1 1 group 1: edge 5 timing data [9:0] = 0x3ff 1 1 2a group 2: edge 0 timing data [9:0] = 0x0a0 0 1 group 2: edge 1 timing data [9:0] = 0x3ff 1 1 2b group 2: edge 2 timing data [9:0] = 0x3ff 1 1 group 2: edge 3 timing data [9:0] = 0x3ff 1 1 2c group 2: edge 4 timing data [9:0] = 0x3ff 1 1 group 2: edge 5 timing data [9:0] = 0x3ff 1 1 3a group 3: edge 0 timing data [9:0] = 0x3ff 1 1 group 3: edge 1 timing data [9:0] = 0x3ff 1 1 3b group 3: edge 2 timing data [9:0] = 0x3ff 1 1 group 3: edge 3 timing data [9:0] = 0x3ff 1 1 3c group 3: edge 4 timing data [9:0] = 0x3ff 1 1 group 3: edge 5 timing data [9:0] = 0x3ff 1 1 4a group 4: edge 0 timing data [9:0] = 0x3ff 1 1 group 4: edge 1 timing data [9:0] = 0x3ff 1 1 4b group 4: edge 2 timing data [9:0] = 0x3ff 1 1 group 4: edge 3 timing data [9:0] = 0x3ff 1 1 4c group 4: edge 4 timing data [9:0] = 0x3ff 1 1 group 4: edge 5 timing data [9:0] = 0x3ff 1 1 5a group 5: edge 0 timing data [9:0] = 0x3ff 1 1 group 5: edge 1 timing data [9:0] = 0x3ff 1 1 5b group 5: edge 2 timing data [9:0] = 0x3ff 1 1 group 5: edge 3 timing data [9:0] = 0x3ff 1 1 5c group 5: edge 4 timing data [9:0] = 0x3ff 1 1 group 5: edge 5 timing data [9:0] = 0x3ff 1 1 maxim integrated 72 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
ecg interrupt driven normal mode example in this example, the c reads back ecg and pace data in response to eint being asserted and interrupting the c via intb or int2b and that efit=8. for the samples given, the following spi transactions might result: the example below will read back complete and correct results but better use could be made of the ecg etag and pace information to realize more efficient c communications. table 55. ecg fifo and pace register read back example (eint, normal mode) cmd fifo index fifo data d[23:0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ecg sample voltage data [17:0] etag[2:0] ptag[2:0] 0x21 ecg 8 ecg sample 08 voltage data [17:0] = 0x008 0 0 0 1 1 1 0x21 ecg 9 ecg sample 09 voltage data [17:0] = 0x009 0 0 0 1 1 1 0x21 ecg 10 ecg sample 10 voltage data [17:0] = 0x00a 0 0 0 0 0 1 0x21 ecg 11 ecg sample 11 voltage data [17:0] = 0x00b 0 0 0 0 1 0 0x21 ecg 12 ecg sample 12 voltage data [17:0] = 0x00c 0 0 0 1 1 1 0x21 ecg 13 ecg sample 13 voltage data [17:0] = 0x00d 0 0 0 1 1 1 0x21 ecg 14 ecg sample 14 voltage data [17:0] = 0x00e 0 0 0 1 1 1 0x21 ecg 15 ecg sample 15 voltage data [17:0] = 0x00f 0 1 0 1 1 1 0x21 ecg -- ecg empty voltage data [17:0] = 0x000 1 1 0 1 1 1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 edge timing data segment [9:0] rfb lst edge timing data segment [9:0] rfb lst 0x35 pace 1a group 1: edge 0 timing data [9:0] = 0x100 1 0 group 1: edge 1 timing data [9:0] = 0x108 0 0 0x36 pace 1b group 1: edge 2 timing data [9:0] = 0x110 1 1 group 1: edge 3 timing data [9:0] = 0x3ff 1 1 0x37 pace 1c group 1: edge 4 timing data [9:0] = 0x3ff 1 1 group 1: edge 5 timing data [9:0] = 0x3ff 1 1 0x39 pace 2a group 2: edge 0 timing data [9:0] = 0x3ff 0 1 group 2: edge 1 timing data [9:0] = 0x3ff 1 1 0x3a pace 2b group 2: edge 2 timing data [9:0] = 0x3ff 1 1 group 2: edge 3 timing data [9:0] = 0x3ff 1 1 0x3b pace 2c group 2: edge 4 timing data [9:0] = 0x3ff 1 1 group 2: edge 5 timing data [9:0] = 0x3ff 1 1 maxim integrated 73 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
the example transactions below will read back identical results, but c communication efficiency is improved by only reading back necessary locations, as indicated by the ecg etag and pace lst bits. table 56. ecg fifo and pace register read back example (eint, normal mode, reduced transactions) cmd fifo index fifo data d[23:0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ecg sample voltage data [17:0] etag[2:0] ptag[2:0] 0x21 ecg 8 ecg sample 08 voltage data [17:0] = 0x008 0 0 0 1 1 1 0x21 ecg 9 ecg sample 09 voltage data [17:0] = 0x009 0 0 0 1 1 1 0x21 ecg 10 ecg sample 10 voltage data [17:0] = 0x00a 0 0 0 0 0 1 0x21 ecg 11 ecg sample 11 voltage data [17:0] = 0x00c 0 0 0 0 1 0 0x21 ecg 12 ecg sample 12 voltage data [17:0] = 0x00d 0 0 0 1 1 1 0x21 ecg 13 ecg sample 13 voltage data [17:0] = 0x00e 0 0 0 1 1 1 0x21 ecg 14 ecg sample 14 voltage data [17:0] = 0x00f 0 0 0 1 1 1 0x21 ecg 15 ecg sample 15 voltage data [17:0] = 0x00f 0 1 0 1 1 1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 edge timing data segment [9:0] rfb lst edge timing data segment [9:0] rfb lst 0x35 pace 1a group 1: edge 0 timing data [9:0] = 0x100 1 0 group 1: edge 1 timing data [9:0] = 0x108 0 0 0x36 pace 1b group 1: edge 2 timing data [9:0] = 0x110 1 1 group 1: edge 3 timing data [9:0] = 0x3ff 1 1 0x39 pace 2a group 2: edge 0 timing data [9:0] = 0x0a0 0 1 group 2: edge 1 timing data [9:0] = 0x3ff 1 1 maxim integrated 74 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
pace interrupt driven normal mode example in this example, the c reads back data in response to pint, which will be asserted in response to the two detected pace events (before eint will be issued since the efit=8 threshold is not met). note the ecg information should still be read first in order to properly locate the pace events in time. for the samples given, the following spi transactions might result (note: other combinations of etags are possible depending on the state of the ecg fifo when the pint interrupts were serviced). table 57. ecg fifo and pace register read back example (pint, normal mode) reg fifo index fifo data d[23:0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ecg sample voltage data [17:0] etag[2:0] ptag[2:0] 0x21 ecg 8 ecg sample 08 voltage data [17:0] = 0x008 0 0 0 1 1 1 0x21 ecg 9 ecg sample 09 voltage data [17:0] = 0x009 0 0 0 1 1 1 0x21 ecg 10 ecg sample 10 voltage data [17:0] = 0x00a 0 0 0 0 0 1 edge timing data segment [9:0] rfb lst edge timing data segment [9:0] rfb lst 0x35 pace 1a group 1: edge 0 timing data [9:0] = 0x100 1 0 group 1: edge 1 timing data [9:0] = 0x108 0 0 0x36 pace 1b group 1: edge 2 timing data [9:0] = 0x110 1 1 group 1: edge 3 timing data [9:0] = 0x3ff 1 1 0x37 pace 1c group 1: edge 4 timing data [9:0] = 0x3ff 1 1 group 1: edge 5 timing data [9:0] = 0x3ff 1 1 ecg sample voltage data [17:0] etag[2:0] ptag[2:0] 0x21 ecg 11 ecg sample 11 voltage data [17:0] = 0x00b 0 0 0 0 1 0 edge timing data segment [9:0] rfb lst edge timing data segment [9:0] rfb lst 0x39 pace 2a group 2: edge 0 timing data [9:0] = 0x0a0 0 1 group 2: edge 1 timing data [9:0] = 0x3ff 1 1 0x3a pace 2b group 2: edge 2 timing data [9:0] = 0x3ff 1 1 group 2: edge 3 timing data [9:0] = 0x3ff 1 1 0x3b pace 2c group 2: edge 4 timing data [9:0] = 0x3ff 1 1 group 2: edge 5 timing data [9:0] = 0x3ff 1 1 ecg sample voltage data [17:0] etag[2:0] ptag[2:0] 0x21 ecg 12 ecg sample 12 voltage data [17:0] = 0x00d 0 0 0 1 1 1 0x21 ecg 13 ecg sample 13 voltage data [17:0] = 0x00d 0 0 0 1 1 1 0x21 ecg 14 ecg sample 14 voltage data [17:0] = 0x00e 0 0 0 1 1 1 0x21 ecg 15 ecg sample 15 voltage data [17:0] = 0x00f 0 1 0 1 1 1 0x21 ecg -- ecg empty voltage data [17:0] = 0x000 1 1 0 1 1 1 maxim integrated 75 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
in the example above, the c will read back complete and correct results but better use could be made of the ecg etag and pace information to realize more efficient c communications as shown below. the example transactions above will read back identical results, but the efficiency is improved by only reading back loca - tions indicated by the ecg etag and pace lst bits. table 58. ecg fifo and pace register read back example (pint, normal mode, reduced transactions) reg fifo index fifo data d[23:0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ecg sample voltage data [17:0] etag[2:0] ptag[2:0] 0x21 ecg 8 ecg sample 08 voltage data [17:0] = 0x008 0 0 0 1 1 1 0x21 ecg 9 ecg sample 09 voltage data [17:0] = 0x009 0 0 0 1 1 1 0x21 ecg 10 ecg sample 10 voltage data [17:0] = 0x00a 0 0 0 0 0 1 edge timing data segment [9:0] rfb lst edge timing data segment [9:0] rfb lst 0x35 pace 1a group 1: edge 0 timing data [9:0] = 0x100 1 0 group 1: edge 1 timing data [9:0] = 0x108 0 0 0x36 pace 1b group 1: edge 2 timing data [9:0] = 0x110 1 1 group 1: edge 3 timing data [9:0] = 0x3ff 1 1 ecg sample voltage data [17:0] etag[2:0] ptag[2:0] 0x21 ecg 11 ecg sample 11 voltage data [17:0] = 0x00b 0 0 0 0 1 0 edge timing data segment [9:0] rfb lst edge timing data segment [9:0] rfb lst 0x39 pace 2a group 2: edge 0 timing data [9:0] = 0x0a0 0 1 group 2: edge 1 timing data [9:0] = 0x3ff 1 1 ecg sample voltage data [17:0] etag[2:0] ptag[2:0] 0x21 ecg 12 ecg sample 12 voltage data [17:0] = 0x00c 0 0 0 1 1 1 0x21 ecg 13 ecg sample 13 voltage data [17:0] = 0x00d 0 0 0 1 1 1 0x21 ecg 14 ecg sample 14 voltage data [17:0] = 0x00e 0 0 0 1 1 1 0x21 ecg 15 ecg sample 15 voltage data [17:0] = 0x00f 0 1 0 1 1 1 maxim integrated 76 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
burst mode example in this example, the c reads data in response to the eint bit and that efit = 8. for the samples given, the following burst mode spi transactions might result. the example burst mode transactions below will read back complete and correct results. note that to achieve this read back in burst mode only three commands are issued: ecg burst 8 + (9 x 24) sclk cycles, pace group 1 burst 8 + (3 x 24) sclk cycles, and pace group 2 burst 8 + (3 x 24) sclk cycles; however, better use could be made of the ecg etag and pace information to realize more efficient c communications. table 59. ecg fifo and pace register read back example (eint, burst mode) reg fifo index fifo data d[23:0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ecg sample voltage data [17:0] etag[2:0] ptag[2:0] 0x20 ecg 8 ecg sample 08 voltage data [17:0] = 0x008 0 0 0 1 1 1 ecg 9 ecg sample 09 voltage data [17:0] = 0x009 0 0 0 1 1 1 ecg 10 ecg sample 10 voltage data [17:0] = 0x00a 0 0 0 0 0 1 ecg 11 ecg sample 11 voltage data [17:0] = 0x00b 0 0 0 0 1 0 ecg 12 ecg sample 12 voltage data [17:0] = 0x00c 0 0 0 1 1 1 ecg 13 ecg sample 13 voltage data [17:0] = 0x00d 0 0 0 1 1 1 ecg 14 ecg sample 14 voltage data [17:0] = 0x00e 0 0 0 1 1 1 ecg 15 ecg sample 15 voltage data [17:0] = 0x00f 0 1 0 1 1 1 ecg -- ecg empty voltage data [17:0] = 0x000 1 1 0 1 1 1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 edge timing data segment [9:0] rfb lst edge timing data segment [9:0] rfb lst 0x34 pace 1a group 1: edge 0 timing data [9:0] = 0x100 1 0 group 1: edge 1 timing data [9:0] = 0x108 0 0 pace 1b group 1: edge 2 timing data [9:0] = 0x110 1 1 group 1: edge 3 timing data [9:0] = 0x3ff 1 1 pace 1c group 1: edge 4 timing data [9:0] = 0x3ff 1 1 group 1: edge 5 timing data [9:0] = 0x3ff 1 1 0x38 pace 2a group 2: edge 0 timing data [9:0] = 0x0a0 0 1 group 2: edge 1 timing data [9:0] = 0x3ff 1 1 pace 2b group 2: edge 2 timing data [9:0] = 0x3ff 1 1 group 2: edge 3 timing data [9:0] = 0x3ff 1 1 pace 2c group 2: edge 4 timing data [9:0] = 0x3ff 1 1 group 2: edge 5 timing data [9:0] = 0x3ff 1 1 maxim integrated 77 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
the example burst mode transactions below will read back identical results, but the efficiency is improved by only read - ing back locations indicated by the ecg etag and pace lst bits. to achieve this read back in burst mode only three commands are issued: ecg burst 8 + (8 x 24) sclk cycles, pace group 1 burst 8 + (2 x 24) sclk cycles, and pace group 2 burst 8 + 24 sclk cycles. table 60. ecg fifo and pace register read back example (eint, burst mode, reduced transactions) reg fifo index fifo data (d[23:0]) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ecg sample voltage data [17:0] etag[2:0] ptag[2:0] 0x20 ecg 8 ecg sample 08 voltage data [17:0] = 0x008 0 0 0 1 1 1 ecg 9 ecg sample 09 voltage data [17:0] = 0x009 0 0 0 1 1 1 ecg 10 ecg sample 10 voltage data [17:0] = 0x00a 0 0 0 0 0 1 ecg 11 ecg sample 11 voltage data [17:0] = 0x00b 0 0 0 0 1 0 ecg 12 ecg sample 12 voltage data [17:0] = 0x00c 0 0 0 1 1 1 ecg 13 ecg sample 13 voltage data [17:0] = 0x00d 0 0 0 1 1 1 ecg 14 ecg sample 14 voltage data [17:0] = 0x00e 0 0 0 1 1 1 ecg 15 ecg sample 15 voltage data [17:0] = 0x00f 0 1 0 1 1 1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 edge timing data segment [9:0] rfb lst edge timing data segment [9:0] rfb lst 0x34 pace 1a group 1: edge 0 timing data [9:0] = 0x100 1 0 group 1: edge 1 timing data [9:0] = 0x108 0 0 pace 1b group 1: edge 2 timing data [9:0] = 0x110 1 1 group 1: edge 3 timing data [9:0] = 0x3ff 1 1 0x38 pace 2a group 2: edge 0 timing data [9:0] = 0x0a0 0 1 group 2: edge 1 timing data [9:0] = 0x3ff 1 1 maxim integrated 78 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
resulting data record example in this example, the c reads data in response to eint and that efit=8. for the complete fifo samples given and the resulting two interrupts, the following spi transactions might have resulted (starting from the beginning of the fifo record). table 61. complete read back example (eint, normal mode) reg fifo index fifo data (d[23:0]) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ecg sample voltage data [17:0] etag[2:0] ptag[2:0] 0x21 ecg 0 ecg sample 00 voltage data [17:0] = 0x000 0 0 1 1 1 1 0x21 ecg 1 ecg sample 01 voltage data [17:0] = 0x001 0 0 1 1 1 1 0x21 ecg 2 ecg sample 02 voltage data [17:0] = 0x002 0 0 0 1 1 1 0x21 ecg 3 ecg sample 03 voltage data [17:0] = 0x003 0 0 0 1 1 1 0x21 ecg 4 ecg sample 04 voltage data [17:0] = 0x004 0 0 0 1 1 1 0x21 ecg 5 ecg sample 05 voltage data [17:0] = 0x005 0 0 0 0 0 0 0x21 ecg 6 ecg sample 06 voltage data [17:0] = 0x006 0 0 0 1 1 1 0x21 ecg 7 ecg sample 07 voltage data [17:0] = 0x007 0 1 0 1 1 1 0x21 ecg -- ecg empty voltage data [17:0] = 0x000 1 1 0 1 1 1 edge timing data segment [9:0] rfb lst edge timing data segment [9:0] rfb lst 0x31 pace 0a group 0: edge 0 timing data [9:0] = 0x000 1 0 group 0: edge 1 timing data [9:0] = 0x011 0 0 0x32 pace 0b group 0: edge 2 timing data [9:0] = 0x022 1 0 group 0: edge 3 timing data [9:0] = 0x033 0 1 0x33 pace 0c group 0: edge 4 timing data [9:0] = 0x3ff 1 1 group 0: edge 5 timing data [9:0] = 0x3ff 1 1 ecg sample voltage data [17:0] etag[2:0] ptag[2:0] 0x21 ecg 8 ecg sample 08 voltage data [17:0] = 0x008 0 0 0 1 1 1 0x21 ecg 9 ecg sample 09 voltage data [17:0] = 0x009 0 0 0 1 1 1 0x21 ecg 10 ecg sample 10 voltage data [17:0] = 0x00a 0 0 0 0 0 1 0x21 ecg 11 ecg sample 11 voltage data [17:0] = 0x00b 0 0 0 0 1 0 0x21 ecg 12 ecg sample 12 voltage data [17:0] = 0x00c 0 0 0 1 1 1 0x21 ecg 13 ecg sample 13 voltage data [17:0] = 0x00d 0 0 0 1 1 1 0x21 ecg 14 ecg sample 14 voltage data [17:0] = 0x00e 0 0 0 1 1 1 0x21 ecg 15 ecg sample 15 voltage data [17:0] = 0x00f 0 1 0 1 1 1 0x21 ecg -- ecg empty voltage data [17:0] = 0x000 1 1 0 1 1 1 edge timing data segment [9:0] rfb lst edge timing data segment [9:0] rfb lst 0x35 pace 1a group 1: edge 0 timing data [9:0] = 0x100 1 0 group 1: edge 1 timing data [9:0] = 0x108 0 0 0x36 pace 1b group 1: edge 2 timing data [9:0] = 0x110 1 1 group 1: edge 3 timing data [9:0] = 0x3ff 1 1 0x37 pace 1c group 1: edge 4 timing data [9:0] = 0x3ff 1 1 group 1: edge 5 timing data [9:0] = 0x3ff 1 1 0x39 pace 2a group 2: edge 0 timing data [9:0] = 0x0a0 0 1 group 2: edge 1 timing data [9:0] = 0x3ff 1 1 0x3a pace 2b group 2: edge 2 timing data [9:0] = 0x3ff 1 1 group 2: edge 3 timing data [9:0] = 0x3ff 1 1 0x3b pace 2c group 2: edge 4 timing data [9:0] = 0x3ff 1 1 group 2: edge 5 timing data [9:0] = 0x3ff 1 1 maxim integrated 79 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
the c must now prepare a complete record of the ecg waveform given the data observed thus far. all empty samples, which do not represent valid ecg time steps or valid pace edges, will be filtered out. then the pace edges will be interleaved within the appropriate ecg sample intervals. for purposes of this example, assume fmstr[1:0] = 01 and ecg_rate[1:0] = 10 (in cnfg_ gen and cnfg_ecg registers, respectively), thus: f ecg = 125sps t ecg = 1/f ecg = 8ms f pace = 64,000hz pace_res = 1/ f pace = 15.625s table 62. example post-processed ecg and pace record time (ms) voltage (lsbs) f* c** p*** note 0.000 0x000 fast mode engaged C ecg voltage may be invalid 8.000 0x001 fast mode engaged C ecg voltage may be invalid 16.000 0x002 24.000 0x003 32.000 0x004 40.000 0x005 pace edge(s) detected during current sample interval - ecg voltage may be impacted 40.000 pace rising edge detected ( 0*15.625s = 0.000ms delayed) 40.266 pace falling edge detected (17*15.625s = 0.256ms delayed) 40.531 pace rising edge detected (34*15.625s = 0.531ms delayed) 40.797 pace falling edge detected (51*15.625s = 0.797ms delayed) 48.000 0x006 pace edge(s) detected during preceding sample interval - ecg voltage may be impacted 56.000 0x007 64.000 0x008 72.000 0x009 80.000 0x00a pace edge(s) detected during current sample interval - ecg voltage may be impacted 84.000 pace rising edge detected (256*15.625s = 4.000ms delayed) 84.125 pace falling edge detected (264*15.625s = 4.125ms delayed) 84.250 pace rising edge detected (272*15.625s = 4.250ms delayed) 88.000 0x00b pace edge(s) detected during preceding & current sample interval - ecg voltage may be impacted 90.500 pace falling edge detected (160*15.625s = 2.500ms delayed) 96.000 0x00c pace edge(s) detected during preceding sample interval - ecg voltage may be impacted 104.000 0x00d 112.000 0x00e 120.000 0x00f *f = fast mode **c = sample corrupted by pace activity ***p = pace edge maxim integrated 80 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
figure 17a. two-electrode ecg and respiration monitor typical application circuit ecgp ecgn capp capn MAX30001 dgnd agnd csb sdi sclk sdo intb int2b fclk mcu csb mosi sclk miso intb int2b fclk vcm vbg vref drvp drvn rbias 10f 1f 10f aout 324k? cpll 1nf 47nf 47nf 1f 200k? 200k? 2nf 10pf electrodes 10pf 200? 200? 47pf 10pf 10pf bip bin avdd dvdd ovdd 0.1f 10f 0.1f 10f 1.1v to 2.0v 1.65v to 3.6v typical application circuits maxim integrated 81 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
figure 17b. four-electrode ecg and respiration monitor typical application circuit ecgp ecgn capp capn MAX30001 dgnd agnd csb sdi sclk sdo intb int2b fclk mcu csb mosi sclk miso intb int2b fclk vcm vbg vref drvp drvn rbias 10f 1f 10f aout 324k? cpll 1nf 47nf 47nf 1f 200k? 200k? 2nf 10pf electrodes 10pf 200? 200? 47pf 10pf 10pf bip bin avdd dvdd ovdd 0.1f 10f 0.1f 10f 1.1v to 2.0v 1.65v to 3.6v typical application circuits (continued) maxim integrated 82 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
application diagrams see figure 18 for an example of a clinical application for monitoring ecg and respiration using just two electrodes and with optional shared defibrillation protection circuitry. the electrode models are shown to illustrate the electrical characteristics of the physical electrodes. four electrode ecg and respiration monitoring application see figure 19 for an example of a clinical application for monitoring ecg and respiration using four electrodes and with optional defibrillation protection circuitry. the electrode models are shown to illustrate the electrical characteristics of the physical electrodes. figure 18. two electrode ecg and respiration monitoring with optional common defibrillation protection. MAX30001 physical electrodes pcb electrode models r body optional defib protection ecgp ecgn capp capn drvp drvn bip bin external emi filters maxim integrated 83 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
figure 19. four electrode ecg and respiration monitoring with optional defibrillation protection. max 30001 physical electrodes pcb electrode models r body optional defib protection ecgp ecgn capp capn drvp drvn bip bin external emi filters maxim integrated 84 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
+ denotes lead(pb)-free/rohs-compliant package. t = tape and reel. * future product. contact factory for availability. ** ep = exposed pad. part temp range pin-package MAX30001cti+* 0oc to +70oc 28 tqfn-ep** MAX30001cti+t* 0oc to +70oc 28 tqfn-ep** MAX30001cwv+ 0oc to +70oc 30wlp MAX30001cwv+t 0oc to +70oc 30wlp package type package code outline no. land pattern no. 28-tqfn t2855+8 21-0140 90-0028 30 wlp w302l2+1 21-100074 refer to application note 1891 ordering information chip information process: cmos package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. maxim integrated 85 MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe www.maximintegrated.com
revision number revision date description pages changed 0 8/17 initial release 1 9/17 added fgures and updated tables 1C86 revision history ? 2017 maxim integrated products, inc. 86 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. MAX30001 ultra-low-power, single-channel integrated biopotential (ecg, r-to-r, and pace detection) and bioimpedance (bioz) afe for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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